Diodes Incorporated PI6LC48C21LIE

Overview

PI6LC48C21LIE from Pericom is a single-output LVCMOS clock synthesizer optimized for Ethernet reference clock generation, using a 25 MHz fundamental-mode crystal to produce 125 MHz (or 130 MHz with 26 MHz crystal) with 0.15 ps typical RMS phase jitter (1.875 MHz–20 MHz offset), full 3.3 V/2.5 V supply support, and industrial temperature operation (−40 °C to +85 °C).

For engineers reviewing the PI6LC48C21LIE datasheet, PI6LC48C21LIE pinout, PI6LC48C21LIE application, or PI6LC48C21LIE equivalent, key selection criteria include low-jitter 125 MHz LVCMOS output, OE-controlled output enable/disable, separate analog/digital power domains (VDDA/VDD), 8-pin TSSOP package compatibility, and crystal interface requirements for Ethernet PHY timing.

Technical Context

This device implements a PLL-based frequency synthesizer architecture with integrated VCO and programmable divider (÷25 and ÷5 stages), accepting a 22.4–27.2 MHz fundamental crystal to generate precise 125 MHz or 130 MHz LVCMOS outputs. It features dual power domains-VDDA for analog PLL circuitry and VDD for digital logic-to isolate switching noise and preserve jitter performance.

The OE pin provides asynchronous output enable/disable control with internal pull-up, while XTAL_IN/XTAL_OUT support parallel-resonant crystals (18 pF load capacitance recommended) or AC-coupled LVCMOS input. Output duty cycle is tightly controlled at 47–53% across temperature and voltage.

Key Specifications

Pinout & Package

Package: 8-pin TSSOP (173 mil width), Pb-free and RoHS-compliant (LIE suffix). Pinout validated per Pericom Rev. B datasheet (08/04/15) and mechanical drawing PD-1308 (Rev. F).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar single-output LVCMOS clock synthesizer applications.

Compared with ICS8430I-01T and Si51212-D-CM125, the PI6LC48C21LIE delivers optimal cost-performance balance for fixed 125 MHz Ethernet PHY timing, with integrated OE control and lower jitter than legacy alternatives-making it ideal for volume industrial switch deployments.

Availability

PI6LC48C21LIE is available at Aetrix Electronics and suitable for Gigabit Ethernet switch PHYs, 10-Gigabit Ethernet NICs, and industrial Ethernet I/O modules requiring stable component supply, lead-free compliance, and industrial temperature assurance.

Supply support for PI6LC48C21LIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, signal integrity, and interface solutions for networking and communications infrastructure.

The PI6LC48C21 belongs to the HiFlex family-designed specifically for low-jitter, single-output clock synthesis in Ethernet physical layer applications where simplicity, reliability, and jitter performance are critical.

FAQ

Can the PI6LC48C21LIE operate with a 26 MHz crystal?

Yes. The device supports 26 MHz crystals to generate 130 MHz output via its internal ÷5 and ÷25 divider chain. Datasheet Table "Output Frequency vs Crystal Frequency" explicitly lists 26 MHz → 130 MHz. Crystal ESR must remain ≤50 Ω and load capacitance matched to 18 pF for guaranteed startup and jitter performance.

Is external termination required on the CLK output?

No. The PI6LC48C21LIE's LVCMOS output has 15 Ω nominal impedance and is designed to drive standard 50 Ω transmission lines directly with proper PCB trace impedance control. Series termination is unnecessary unless trace length exceeds 3 inches or signal integrity simulations indicate ringing.

What happens if VDDA and VDD are shorted together?

Shorting VDDA and VDD degrades RMS phase jitter by up to 2× (e.g., 0.15 ps → ~0.3 ps) due to coupling of digital switching noise into the analog PLL domain. Pericom's layout guidelines require separate vias, dedicated 0.1 µF bypass caps per supply, and a 10 Ω + 10 µF RC filter on VDDA to maintain specified jitter performance.

Does the OE pin support hot-plug or dynamic clock gating?

Yes. OE is asynchronous and fully static-asserting low places CLK in high-impedance state within 10 ns (max propagation delay), with no glitches or metastability. This enables safe clock gating during FPGA reconfiguration or PHY power-down sequences without requiring synchronization logic.