Diodes Incorporated PI6LC48C51LIE

Overview

PI6LC48C51LIE from Pericom Semiconductor is a single-output LVCMOS clock generator optimized for Ethernet, SONET/SDH, and SATA/SAS reference clock generation. It accepts 17.5–21.25 MHz fundamental-mode crystals and delivers 70–170 MHz output with 0.2 ps typical RMS phase jitter at 155.52 MHz (1.875 MHz–20 MHz offset), operating from 2.5 V or 3.3 V supplies across –40°C to +85°C.

For engineers reviewing the PI6LC48C51LIE datasheet, PI6LC48C51LIE pinout, PI6LC48C51LIE application, or PI6LC48C51LIE equivalent, key selection criteria include its dual-supply compatibility, industrial temperature range, low-jitter synthesis architecture, frequency select (FS) control, and OE-enabled output tri-state capability.

Technical Context

The PI6LC48C51LIE integrates a PLL-based frequency synthesizer with a 32× integer divider in the feedback path and programmable output dividers controlled by the FS pin. Its analog VDDA and digital VDD supplies are physically separated to minimize supply-induced jitter coupling into the VCO and output buffer.

It supports crystal input via parallel-resonant 18 pF load-capacitance crystals (e.g., FLxxxx or FYxxxxx series), with internal pull-up/pull-down resistors (51 kΩ) on OE and FS pins. The XTAL_IN accepts AC-coupled LVCMOS signals down to 10 ns edge rate, while XTAL_OUT may be left floating when using external clock sources.

Key Specifications

Pinout & Package

PI6LC48C51LIE is housed in an 8-pin lead-free TSSOP (Package Code L, 173 mil width), with exposed pad not electrically connected. Power separation between VDD (digital core) and VDDA (analog PLL/VCO) is critical for jitter performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with IDT 8T49N241 and Si5338A-A-GM, the PI6LC48C51LIE offers lowest BOM cost and simplest layout for fixed-frequency, single-output Ethernet/SONET/SATA applications-no configuration, no EEPROM, no I²C stack-while maintaining sub-0.25 ps jitter performance.

Availability

PI6LC48C51LIE is available at Aetrix Electronics and suitable for Ethernet switching systems, SONET/SDH line cards, and SATA/SAS storage controllers requiring stable component supply across extended industrial temperature ranges and long production lifecycles.

Supply support for PI6LC48C51LIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, signal integrity, and interface ICs for communications and computing infrastructure.

The PI6LC48C51 belongs to the HiFlex family-designed specifically for low-jitter, crystal-based clock synthesis in cost-sensitive, high-volume networking and storage platforms where simplicity and jitter performance are jointly critical.

FAQ

Can PI6LC48C51LIE operate with a 25 MHz crystal?

No. The device is characterized and guaranteed only for 17.5–21.25 MHz fundamental-mode crystals. Using a 25 MHz crystal exceeds the specified crystal frequency range and may cause startup failure, frequency inaccuracy, or increased phase jitter due to overtone mode excitation or ESR mismatch.

What is the purpose of the 10 Ω resistor in the VDDA filter network?

The 10 Ω resistor isolates the analog VDDA supply from digital switching noise on the main VDD rail. Combined with the 10 µF capacitor, it forms an RC low-pass filter that attenuates high-frequency noise above ~1.6 kHz, preserving VCO stability and minimizing jitter contribution from digital supply transients.

Is the OE pin functional during power-up or brown-out conditions?

Yes. OE has an internal 51 kΩ pull-up resistor, ensuring the CLK output remains in high-impedance state until VDD and VDDA stabilize and OE is actively driven high. This prevents spurious clock edges during power sequencing, protecting downstream SerDes receivers from invalid timing.

Does PI6LC48C51LIE support spread-spectrum clocking (SSC)?

No. The PI6LC48C51LIE does not implement spread-spectrum modulation. It is a fixed-frequency, low-jitter synthesizer optimized for applications requiring deterministic timing-such as Ethernet PHYs and SONET framers-where SSC would violate jitter compliance limits and introduce data-dependent eye closure.