Diodes Incorporated PI6LC48C51LIEX

Overview

PI6LC48C51LIEX from Pericom Semiconductor is a single-output LVCMOS clock synthesizer optimized for Ethernet, SONET/SDH, and SATA/SAS reference clock generation. It supports 70–170 MHz output frequencies, delivers 0.2 ps typical RMS phase jitter at 155.52 MHz (1.875 MHz–20 MHz), operates from 3.3 V or 2.5 V supplies, and is rated for industrial temperature (−40 °C to +85 °C) in an 8-pin TSSOP package.

For engineers reviewing the PI6LC48C51LIEX datasheet, PI6LC48C51LIEX pinout, PI6LC48C51LIEX application, or PI6LC48C51LIEX equivalent, key selection criteria include its low-jitter synthesis capability, dual-supply compatibility, frequency select (FS) control logic, OE-enabled output tri-state, and crystal interface requirements for 17.5–21.25 MHz fundamental-mode crystals with 18 pF load capacitance.

Technical Context

The PI6LC48C51LIEX integrates a PLL-based frequency synthesizer with a programmable divider chain and a 32× internal VCO multiplier. Its architecture accepts a fundamental-mode crystal (17.5–21.25 MHz) and generates precise Ethernet (156.25 MHz), SONET OC-3/12 (155.52 MHz), or SATA (100 MHz, 150 MHz) reference clocks via FS-selectable integer-N division ratios.

It features separate analog (VDDA) and core (VDD) power domains with dedicated bypassing-VDDA requires a 10 Ω series resistor and 10 μF capacitor to suppress PLL noise coupling-while the OE pin enables hardware-controlled output disable with internal pull-up, and FS selects between two preconfigured output frequencies per crystal input.

Key Specifications

Pinout & Package

Package: 8-pin TSSOP (L), 173 mil width, Pb-free & RoHS-compliant, tape-and-reel (X suffix).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock synthesizer applications.

Compared with IDT 8T49N241 and Si5338A-D-GM, the PI6LC48C51LIEX offers simpler hardware-only configuration, smaller 8-TSSOP footprint, and lower BOM cost for single-clock Ethernet/SONET/SATA applications where fixed-frequency synthesis suffices.

Availability

PI6LC48C51LIEX is available at Aetrix Electronics and suitable for Ethernet switch timing, SONET line cards, SATA host controllers, and industrial storage servers requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PI6LC48C51LIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (now part of Diodes Incorporated) specialized in high-performance clock management, signal integrity, and interface solutions for communications and computing markets.

The PI6LC48C51LIEX belongs to the HiFlex family-designed specifically for low-jitter, single-output clock synthesis in wired infrastructure applications including Ethernet, optical transport, and serial storage interfaces.

FAQ

What crystal specifications are mandatory for stable operation?

The PI6LC48C51LIEX requires a fundamental-mode, parallel-resonant crystal with 17.5–21.25 MHz frequency, 18 pF load capacitance, ≤50 Ω ESR, and ≤1 mW drive level. Pericom recommends FLxxxx (3.2×2.5 mm) or FYxxxxx (5×3.2 mm) series crystals with ±20 ppm or ±30 ppm tolerance. Deviations outside these specs risk start-up failure or increased jitter.

Can the XTAL_IN pin accept an LVCMOS clock instead of a crystal?

Yes-XTAL_IN supports AC-coupled LVCMOS clock inputs with edge rates ≥10 ns. The XTAL_OUT pin must be left floating in this mode. Amplitude should be reduced to half-swing (e.g., 1.25 Vpp for 2.5 V supply) to minimize rail coupling noise, and termination (e.g., 50 Ω to VDD/2) is required at the driver side to match transmission line impedance.

How does the FS pin affect output frequency selection?

The FS pin selects between two preprogrammed output frequencies per crystal input: FS = low selects the higher output (e.g., 156.25 MHz with 19.53125 MHz crystal), FS = high selects the lower output (e.g., 78.125 MHz). The mapping is fixed per crystal frequency and defined in the Output Frequency Table; no external programming is needed.

What is the purpose of separating VDD and VDDA supplies?

VDD powers digital logic (OE, FS, dividers), while VDDA powers the analog PLL/VCO. Separation prevents switching noise from digital circuits from modulating the VCO, which would increase phase jitter. The VDDA rail requires a 10 Ω resistor + 10 μF capacitor for enhanced PSRR, whereas VDD uses only 0.1 μF bypassing-this architecture achieves <0.25 ps jitter at 77.76 MHz.