Diodes Incorporated PI6LC48H02-01LIE

Overview

PI6LC48H02-01LIE from Diodes Incorporated (acquired Pericom) is a PCIe 3.0/2.0/1.0-compliant clock generator with dual HCSL differential outputs, accepting a 25 MHz crystal or single-ended clock input and generating 25/100/125/200 MHz outputs. It features 0.32 ps RMS phase jitter at 100 MHz, 3.3 V ±10% supply, and industrial temperature range (–40°C to +85°C), deployed in server motherboard clock trees.

For engineers reviewing the PI6LC48H02-01LIE datasheet, PI6LC48H02-01LIE pinout, PI6LC48H02-01LIE application, or PI6LC48H02-01LIE equivalent, key selection criteria include PCIe 3.0 phase jitter compliance (0.45 ps RMS high-frequency), HCSL output drive strength (6×IREF), output enable timing (10 µs), and dual-output skew control (50 ps max).

Technical Context

The device implements a proprietary PLL architecture optimized for PCIe reference clock synthesis, locking to a 25 MHz fundamental-mode crystal and generating two independent HCSL output pairs with selectable frequencies via S1:S0 control pins. Its analog core includes dedicated VDDA/GNDA rails and an IREF pin for precision current-setting (475 Ω → 2.32 mA → 13.9 mA per HCSL leg).

Output structure is open-source HCSL: each CLKx/CLKx̅ pair requires external series termination (33 Ω) and ground-return resistors (49.9 Ω), supporting 100 Ω differential routing per PCIe Layout Guidelines. Power-down mode (PD#) reduces supply current to 0.15 mA while preserving configuration state.

Key Specifications

Pinout & Package

Package: 16-pin Pb-free Green TSSOP (L16), 4.4 mm × 5.0 mm body, 0.65 mm pitch, JEDEC MO-153 compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generator applications.

Compared with IDT8T49N242BGI and Si53301-B-GM, the PI6LC48H02-01LIE provides native HCSL drive, hardware-selectable frequencies, and lower system-level jitter margin risk for PCIe 3.0 root complex designs - without firmware dependency or external memory.

Availability

PI6LC48H02-01LIE is available at Aetrix Electronics and suitable for PCIe 3.0 server motherboards, multi-port Ethernet switches, and industrial embedded systems requiring stable component supply and long-term lifecycle support.

Supply support for PI6LC48H02-01LIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated acquired Pericom Semiconductor in 2017 and maintains its high-performance timing portfolio, focusing on clock generation, distribution, and synchronization ICs for datacenter and communications infrastructure.

The PI6LC48H02-01LIE belongs to Pericom's PCIe-optimized clock generator product line, designed specifically to meet stringent phase jitter, skew, and signal integrity requirements of PCI Express 3.0 root complexes and endpoint devices.

FAQ

What crystal specifications are required for stable operation?

The PI6LC48H02-01LIE requires a 25 MHz fundamental-mode parallel-resonant crystal with load capacitance of 18 pF and frequency tolerance ≤ ±30 ppm over –40°C to +85°C. Recommended part numbers include GC2500003 (49S/SMD) and FL2500047 (3.2×2.5 mm SMD). External load capacitors must be calculated as (CL − 8) × 2 pF.

How is HCSL output termination implemented on the PCB?

HCSL outputs require 33 Ω series resistors placed within 0.2 inches of each CLK pin and 49.9 Ω resistors from each CLKx̅ pin to ground. Differential routing must maintain 100 Ω characteristic impedance over lengths up to 16 inches (microstrip) or 14.4 inches (stripline), per PCIe Layout Guidelines.

Can the device operate with LVDS-compatible voltage levels?

Yes - the PI6LC48H02-01LIE supports LVDS-compatible outputs by configuring external termination: use 100 Ω across CLKx/CLKx̅ and 150 Ω from CLKx̅ to ground (RP = RQ = 100 Ω, RT = 150 Ω). This achieves ~350 mV differential swing, meeting LVDS voltage thresholds without level-shifting ICs.

What is the function of the IREF pin and how is it used?

The IREF pin sources a precision current used to set HCSL output drive strength. A 475 Ω resistor to ground sets IREF = 2.32 mA, resulting in 6×IREF = 13.9 mA per HCSL output leg. This defines the 0.8 V current-mode output voltage swing across 50 Ω termination, ensuring consistent edge rate and amplitude across temperature.