Diodes Incorporated PI6LC48H02-01LIEX

Overview

PI6LC48H02-01LIEX from Pericom is a PCIe 3.0/2.0/1.0-compliant clock generator with two HCSL differential output pairs, driven by a 25 MHz crystal or single-ended clock input. It delivers selectable output frequencies of 25 MHz, 100 MHz, 125 MHz, or 200 MHz, supports power-down mode and OE-controlled tri-state, and operates across -40°C to +85°C in industrial environments for server and networking applications.

For engineers reviewing the PI6LC48H02-01LIEX datasheet, PI6LC48H02-01LIEX pinout, PI6LC48H02-01LIEX application, or PI6LC48H02-01LIEX equivalent, key selection criteria include PCIe 3.0 phase jitter compliance (0.45 ps RMS), HCSL/LVDS dual-output compatibility, 3.3 V ±10% supply operation, and 16-pin TSSOP package integration with IREF-based current calibration.

Technical Context

The device implements a proprietary PLL architecture optimized for PCIe 3.0 timing integrity, with low-bandwidth loop filters enabling sub-0.5 ps RMS phase jitter at 100–125 MHz outputs under 12 kHz–20 MHz integration bandwidth. Its dual-output structure provides independent CLK0 and CLK1 HCSL pairs, each with matched rise/fall times (175–700 ps) and <50 ps inter-output skew.

Control logic uses S0/S1 select pins to configure frequency, PD# for hardware power-down, and OE for output enable/disable - all with internal pull-up resistors. The IREF pin sets output current via an external 475 Ω resistor, delivering 2.32 mA reference and 6×IREF (≈13.9 mA) per HCSL source leg, meeting PCI Express HCSL voltage swing (0.175–0.525 V) and termination requirements.

Key Specifications

Pinout & Package

Package: 16-pin Pb-free Green TSSOP (L16), 4.4 mm × 5.0 mm body, 0.65 mm pitch, JEDEC MO-153 compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with IDT8T49N242A and Si53302-A01AGM, the PI6LC48H02-01LIEX offers pin-strapped frequency selection, native HCSL drive capability, and PCIe 3.0-compliant jitter without configuration overhead - making it optimal for cost-sensitive, high-volume server and switch designs.

Availability

PI6LC48H02-01LIEX is available at Aetrix Electronics and suitable for PCIe 3.0 server backplanes, 10G/25G Ethernet switch PHY timing, and industrial embedded computing requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PI6LC48H02-01LIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, signal integrity, and interface solutions for datacenter and communications infrastructure.

The PI6LC48H02-01LIEX belongs to Pericom's PCIe-optimized clock generator product line, designed specifically to meet Gen3 timing margins in space-constrained server and switch PCB layouts with minimal external components.

FAQ

What crystal specifications are required for stable operation?

The PI6LC48H02-01LIEX requires a 25 MHz fundamental-mode parallel-resonant crystal with load capacitance of 18 pF and frequency tolerance ≤±30 ppm over -40°C to +85°C. Recommended part numbers include GC2500003, FY2500091, and FL2500047 - all specified with 18 pF CL and tight stability. External crystal capacitors must be set to (CL − 8) × 2 = 16 pF.

How is HCSL output current calibrated using the IREF pin?

IREF sinks a precision 2.32 mA current when a 475 Ω resistor connects Pin 9 to ground. This sets the internal current reference used to bias the HCSL output drivers, resulting in 6 × IREF ≈ 13.9 mA per source leg. The 0.8 V HCSL swing across 50 Ω termination is achieved only when this exact current is established.

Can the device operate with LVDS signaling instead of HCSL?

Yes - the PI6LC48H02-01LIEX supports LVDS-compatible voltage levels with appropriate board layout: use 100 Ω differential termination, 100 Ω pull-up (RP) and pull-down (RQ) resistors, and route CLK0/CLK1 and CLK1/CLK1 as controlled 100 Ω differential pairs. No register changes are needed; only external termination differs from HCSL mode.

What is the stabilization time after power-up and how does it affect system boot?

tSTABLE is 14 ms from VDD reaching 3.3 V - the time required for the internal PLL to lock and outputs to reach stable frequency and jitter performance. This delay must be accounted for in BIOS/UEFI initialization sequences before PCIe link training begins, especially in fast-boot systems where clock readiness precedes enumeration.