Diodes Incorporated PI6LC48H02LIE

Overview

PI6LC48H02LIE from Diodes Incorporated is a PCIe 4.0/3.0/2.0/1.0-compliant clock generator with two HCSL differential output pairs, operating from a 25MHz crystal input and delivering selectable 25/100/125/200MHz outputs at 3.3V supply. It serves as the primary clock source for PCIe root complexes and endpoints in industrial PCs and embedded computing platforms.

For engineers reviewing the PI6LC48H02LIE datasheet, PI6LC48H02LIE pinout, PI6LC48H02LIE application, or PI6LC48H02LIE equivalent, key selection criteria include PCIe Gen4 RMS phase jitter (0.37–0.45ps), HCSL current-mode drive (0.8V differential pair), dual-output skew (<50ps), and TSSOP-16 industrial temperature support (−40°C to +85°C).

Technical Context

The PI6LC48H02LIE implements a proprietary PLL architecture optimized for PCIe timing compliance, with programmable loop bandwidths (2–5MHz) supporting Gen2/Gen3/Gen4 jitter requirements. Its output frequency is selected via S1:S0 control pins, enabling static configuration without I²C or SPI interface.

It supports both crystal (25MHz fundamental parallel-resonant) and single-ended clock inputs, with internal current reference (IREF pin) enabling precise 6×IREF HCSL output current scaling. Output termination requires external series and ground resistors per PCIe layout guidelines, and LVDS-compatible operation is achievable with reconfigured biasing.

Key Specifications

Pinout & Package

PI6LC48H02LIE is housed in a lead-free, RoHS-compliant 16-pin TSSOP (L16) package measuring 5.0mm × 4.4mm × 1.2mm, with 0.65mm pitch and exposed pad not present. Thermal resistance θ_JA is 90°C/W (still air).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generator applications.

Compared with IDT8T49N242B and Si5332A-D-GM, the PI6LC48H02LIE delivers optimal balance of PCIe Gen4 compliance, minimal external components (no XO needed), and low-power dual-output simplicity-making it ideal for cost-sensitive, high-volume industrial PCIe designs where configurability beyond four frequencies is unnecessary.

Availability

PI6LC48H02LIE is available at Aetrix Electronics and suitable for PCIe 4.0 motherboard design, industrial network switch timing, and embedded NVMe SSD controller applications requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant sourcing.

Supply support for PI6LC48H02LIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for industrial, computing, and communications markets.

The PI6LC48H02LIE belongs to Diodes' Pericom timing product line, engineered specifically for PCI Express infrastructure applications requiring ultra-low jitter, robust ESD immunity (2kV HBM), and seamless drop-in compatibility with legacy PCIe clock trees.

FAQ

What crystal specifications are mandatory for stable PI6LC48H02LIE operation?

The device requires a 25MHz fundamental-mode parallel-resonant crystal with load capacitance of 18pF and frequency tolerance ≤±30ppm over −40°C to +85°C. Recommended part numbers include FL2500038 (3.2×2.5mm, ±20ppm) and GC2500003 (4.0mm HC-49/SMD). External load capacitors must be set to (CL − 8) × 2 = 16pF for CL = 18pF crystals.

How does the IREF pin affect HCSL output drive strength?

The IREF pin sources a precision current that sets the internal current reference. With a 475Ω external resistor, IREF = 2.32mA, and each HCSL output delivers 6 × IREF = 13.9mA into 50Ω loads. This defines the 0.8V differential swing (13.9mA × 50Ω × 2 = 0.695V ≈ 0.8V with margin). Changing R_IREF linearly scales output current and voltage swing.

Can PI6LC48H02LIE be used in LVDS mode, and what layout changes are required?

Yes - configure for LVDS by connecting VDDA to 3.3V, setting OE = HIGH, and using 100Ω differential termination with 150Ω Thevenin bias (RP = RQ = 100Ω, RT = 150Ω) per Diodes' LVDS Layout Guidelines. Rise/fall times increase to ~700ps, and common-mode voltage shifts to ~1.2V. No pin reconfiguration is needed; only external passive changes are required.

What is the maximum allowable trace length between PI6LC48H02LIE and PCIe receiver for HCSL routing?

For HCSL routing, L4 (coupled 100Ω differential microstrip) must be between 2 inches and 16 inches on a single PCB. When routing to a PCIe connector, L4 must be 0.25–14 inches. Total non-coupled trace length (L1+L2+L3) must not exceed 0.9 inches, with individual segments limited to 0.5", 0.2", and 0.2" respectively, to maintain impedance integrity and minimize reflections.