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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Diodes Incorporated PI6LC48H02LIEX

Name: PI6LC48H02LIEX
Brand: Diodes Incorporated
SKU: PI6LC48H02LIEX
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: PI6LC48H02LIEX

Manufacturer:: Diodes Incorporated

Category:: Application Specific Clock/Timing

Package:: 16-TSSOP (0.173", 4.40mm Width)

Datasheet:: PI6LC48H02LIEX.pdf

Description:: IC CLOCK GENERATOR 16TSSOP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

PI6LC48H02LIEX from Diodes Incorporated is a PCIe 4.0/3.0/2.0/1.0-compliant clock generator with two HCSL differential output pairs, operating from a 25MHz crystal input and delivering selectable 25/100/125/200MHz outputs. It features 0.32ps RMS phase jitter at 100MHz, 3.3V ±10% supply, and industrial temperature range (–40°C to +85°C), deployed in PC motherboard and embedded computing timing subsystems.

For engineers reviewing the PI6LC48H02LIEX datasheet, PI6LC48H02LIEX pinout, PI6LC48H02LIEX application, or PI6LC48H02LIEX equivalent, key selection criteria include PCIe Gen4 jitter compliance (0.37–0.45ps RMS), dual HCSL/LVDS output configurability, 16-pin TSSOP package footprint, and OE-controlled tri-state output enable timing (10μs).

Technical Context

The PI6LC48H02LIEX implements a proprietary PLL architecture optimized for PCIe reference clock synthesis, accepting only 25MHz fundamental-mode crystal or single-ended clock input and generating two independent differential output banks with programmable frequency selection via S1:S0 control pins. Its internal current reference (IREF pin) sets HCSL output drive strength (6×IREF) and enables precise 50Ω trace impedance matching.

It supports both HCSL (0.8V current-mode, 800mV swing) and LVDS-compatible voltage-level operation through external termination configuration, with strict layout requirements including <500ps rise/fall times, <50ps inter-output skew, and defined microstrip/stripline routing lengths per PCI Express and LVDS standards.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Frequency	Selectable 25/100/125/200MHz - matches PCIe Gen1–Gen4 and Ethernet reference clock rates.
RMS Phase Jitter (100MHz)	0.32ps (12kHz–20MHz) - meets PCIe Gen4 specification limit of ≤0.5ps for CDR lock stability.
Supply Voltage	3.3V ±10% - compatible with standard I/O rail; requires 0.01μF decoupling per VDD pin.
Output Type	HCSL differential (0.8V current mode) or LVDS-compatible - configurable via external resistors and layout.
Cycle-to-Cycle Jitter	35ps (typ) - ensures low timing uncertainty for high-speed serial link sampling windows.
Operating Temperature	–40°C to +85°C - qualified for industrial-grade embedded and server board deployment.
Package	16-pin TSSOP (173mil wide) - surface-mount footprint with GNDA/VDDA/VDDX separation for analog/digital noise isolation.

Pinout & Package

PI6LC48H02LIEX is housed in a 16-pin TSSOP (L16) package with exposed pad thermal design, measuring 5.0mm × 4.4mm × 1.2mm. Pin 1 is marked by a dot; pins are arranged in two rows (1–8 top, 9–16 bottom), with dedicated analog/digital power (VDDA/GNDA) and core power (VDDX) rails to minimize switching noise coupling into clock outputs.

Pin/Terminal	Circuit Role	Design Meaning
1, 2 (S0, S1)	Frequency select inputs	Binary-coded control lines (internal pull-up) setting output frequency: 00=25MHz, 01=100MHz, 10=125MHz, 11=200MHz.
4 (X1/CLK), 5 (X2)	Crytal/clock interface	X1 accepts 25MHz crystal or single-ended clock; X2 is crystal output (open when using external clock).
6 (OE)	Output enable	Active-low control: pulls all CLK outputs to high-impedance state within 10μs when asserted.
9 (IREF)	Current reference output	Sinks precision current (2.32mA with 475Ω resistor) to set HCSL output drive strength (IOH = 6×IREF).
10, 11, 14, 15 (CLK1, CLK1, CLK0, CLK0)	Differential clock outputs	Two fully independent HCSL pairs (CLK0+/CLK0–, CLK1+/CLK1–); each pair shares crossing-point voltage (250–550mV) and duty cycle (45–55%).
7, 13 (GND, GNDA)	Ground returns	GND = digital ground; GNDA = analog/output ground - must be connected with low-inductance path to avoid jitter degradation.
12, 16 (VDDA, VDDX)	Power supplies	VDDA powers analog/PLL circuitry; VDDX powers output drivers - both require separate 3.3V sources and local 0.01μF decoupling.

Key Features

Feature	Design Value
PCIe Gen4-compliant jitter	0.37ps RMS phase jitter (12kHz–20MHz) at 100MHz output - enables reliable CDR lock in Gen4 receivers without additional cleanup.
Configurable output format	Hardware-selectable HCSL or LVDS-compatible operation via external termination (RS=33Ω/RT=49.9Ω for HCSL; RP=RQ=100Ω for LVDS).
Low-skew dual outputs	≤50ps inter-pair skew at crossing point - maintains timing alignment across PCIe root complex and endpoint clock domains.
Industrial temperature support	Full functionality from –40°C to +85°C with no derating - suitable for fanless edge servers and ruggedized embedded controllers.
Green, lead-free packaging	16-pin TSSOP compliant with RoHS 3, halogen-free (<900ppm Br/Cl, <1000ppm Sb), and IATF 16949 manufacturing.

Applications

PCIe Root Complex Timing

Embedded Computing Backplane Clocking

Use Scenario: Providing synchronized 100MHz reference clocks to CPU PCIe controller and multiple peripheral slots on a server motherboard.

IC Role / Device Role / Timing Role: Primary PCIe Gen4-compliant clock source with dual HCSL outputs routed to root complex and switch upstream port.

Use Value: Meets PCIe Gen4 jitter spec (≤0.5ps RMS) without external jitter cleaners, reducing BOM count and board area.

Use Scenario: Distributing 125MHz clock signals across modular industrial I/O carrier boards with hot-plug PCIe expansion mezzanines.

IC Role / Device Role / Timing Role: Central timing hub generating matched-frequency clocks for FPGA-based PCIe endpoints and real-time Ethernet MACs.

Use Value: Dual independent outputs eliminate need for clock fanout buffers, lowering power (115mA IDD) and inter-signal skew.

Network Interface Card Reference Clock

Storage Controller Synchronization

Use Scenario: Supplying 200MHz reference to 10GbE/25GbE PHYs and PCIe Gen3 x4 NVMe host controllers on a converged NIC.

IC Role / Device Role / Timing Role: Multi-protocol clock generator supporting both Ethernet (125MHz/200MHz) and PCIe (100MHz/200MHz) reference requirements.

Use Value: Single-device solution replaces discrete oscillators and fanout ICs, simplifying layout and improving signal integrity via matched trace routing.

Use Scenario: Driving clock inputs of dual NVMe SSD controllers and RAID ASIC on an enterprise storage backplane.

IC Role / Device Role / Timing Role: Low-jitter, high-drive-strength clock source ensuring deterministic data sampling across parallel flash channels.

Use Value: HCSL output drive (6×IREF) sustains signal integrity over 14-inch coupled stripline traces per PCIe layout guidelines.

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generation applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
IDT8T49N242A	4-output, programmable fractional-N PLL; higher integration but 3.3V-only supply; 0.28ps jitter at 100MHz.	Supports multi-frequency synthesis (not fixed 25/100/125/200MHz); requires external configuration EEPROM.	Choose for flexible frequency planning across mixed-speed PCIe/Ethernet systems where BOM cost is secondary to design reuse.
Si5332A-D-GM	6-output, multi-rate clock generator with integrated crystal; 0.22ps jitter; supports PCIe Gen5; 1.8V/3.3V dual supply.	Includes on-chip MEMS resonator; eliminates external crystal and load caps; higher pin count (32-QFN).	Choose when eliminating crystal placement and tuning effort is critical, and Gen5 readiness is required for future-proofing.

Compared with IDT8T49N242A and Si5332A-D-GM, the PI6LC48H02LIEX offers lower system cost and simpler layout for fixed-frequency PCIe 4.0 designs, trading programmability and ultra-low jitter for proven interoperability, minimal external components, and direct drop-in compatibility with legacy TSSOP-based motherboard footprints.

Availability

PI6LC48H02LIEX is available at Aetrix Electronics and suitable for PCIe 4.0 server motherboards, industrial embedded computing platforms, and network interface card designs requiring stable component supply, long-lifecycle availability, and RoHS-compliant sourcing.

Supply support for PI6LC48H02LIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, headquartered in Plano, Texas, with design centers across Asia and manufacturing in certified ISO/TS 16949 facilities.

The PI6LC48H02LIEX belongs to Diodes' Pericom timing product line, engineered specifically for high-reliability PCIe and Ethernet reference clock distribution in compute and networking infrastructure.

FAQ

What crystal specifications are mandatory for stable PI6LC48H02LIEX operation?

The device requires a 25MHz fundamental-mode parallel-resonant crystal with load capacitance of 18pF and frequency tolerance ≤±30ppm across –40°C to +85°C. Recommended part numbers include GC2500003 (49S/SMD), FY2500107 (5x3.2mm), and FL2500038 (3.2x2.5mm). External crystal capacitors must be set to (CL − 8) × 2 pF - e.g., 16pF for an 18pF crystal.

How does the IREF pin affect HCSL output performance?

The IREF pin sources a precision current used to bias the internal HCSL output drivers. Connecting a 475Ω resistor between IREF and ground sets IREF = 2.32mA, resulting in IOH = 6 × IREF = 13.9mA - which establishes the correct 0.8V current-mode output level and ensures 50Ω trace impedance matching. Deviation alters output voltage swing and jitter.

Can PI6LC48H02LIEX drive LVDS loads without external level-shifting components?

Yes - the PI6LC48H02LIEX supports LVDS-compatible operation natively by reconfiguring external termination: use RP = RQ = 100Ω across the differential pair and RT = 150Ω to ground. This achieves ~350mV differential swing and meets LVDS voltage thresholds without active translators, though layout must follow specified non-coupled trace lengths (L1 ≤ 0.5 inch, L2 ≤ 0.2 inch).

What is the maximum allowable trace length for PCIe-compliant HCSL routing?

For HCSL outputs, the total uncoupled trace length (L1 + L2 + L3) must not exceed 0.9 inches (0.5 + 0.2 + 0.2), while the coupled differential segment (L4) must be 2–16 inches for microstrip or 1.8–14.4 inches for stripline, all targeting 100Ω differential impedance. Exceeding these lengths increases insertion loss and degrades jitter margin below PCIe Gen4 requirements.

PI6LC48H02LIEX Specifications

Product attributes: Attribute value

Manufacturer:: Diodes Incorporated

Series:: -

Package/Case:: 16-TSSOP (0.173", 4.40mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: Yes

Main Purpose:: Ethernet, PCI Express (PCIe)

Input:: Clock, Crystal

Output:: HCSL, LVDS

Number of Circuits:: 1

Ratio - Input:Output:: 1:2

Differential - Input:Output:: No/Yes

Frequency - Max:: 200MHz

Voltage - Supply:: 3V ~ 3.6V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 16-TSSOP

PI6LC48H02LIEX FAQ

1.How can I place an order for PI6LC48H02LIEX through Aetrix?

Please submit a Request for Quotation (RFQ) for PI6LC48H02LIEX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for PI6LC48H02LIEX reliable?

The price and inventory of PI6LC48H02LIEX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PI6LC48H02LIEX is usually 5 days.

3.What payment methods are accepted for PI6LC48H02LIEX?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PI6LC48H02LIEX transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for PI6LC48H02LIEX?

PI6LC48H02LIEX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your PI6LC48H02LIEX order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for PI6LC48H02LIEX?

For technical support, including PI6LC48H02LIEX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PI6LC48H02LIEX requirements.

6.How does Aetrix verify that PI6LC48H02LIEX is sourced from the original manufacturer or authorized distributors?

All PI6LC48H02LIEX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PI6LC48H02LIEX meets industry standards.

7.What is the process for return or replacement of PI6LC48H02LIEX?

All PI6LC48H02LIEX units undergo pre-shipment inspection (PSI). If there is an issue with PI6LC48H02LIEX, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The PI6LC48H02LIEX part is unused and in its original packaging.

Return procedure for PI6LC48H02LIEX:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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