Diodes Incorporated PI6LC48H04LIE

Overview

PI6LC48H04LIE from Diodes Incorporated is a PCIe 4.0/3.0/2.0/1.0 and Ethernet-compliant clock generator with four low-power HCSL differential outputs, designed for high-speed serial interconnect timing in networking and embedded systems. It accepts a 25MHz crystal input and delivers four independent output frequencies-100MHz, 125MHz, 156.25MHz, and 200MHz-with RMS phase jitter as low as 0.3ps (12kHz–20MHz) and PCIe 4.0-compliant 0.45ps RMS jitter.

For engineers reviewing the PI6LC48H04LIE datasheet, PI6LC48H04LIE pinout, PI6LC48H04LIE application, or PI6LC48H04LIE equivalent, key selection criteria include PCIe Gen4 jitter compliance, dual-supply support (3.3V/2.5V), programmable output frequency selection via S[1:0], VSWING_CTRL-adjustable HCSL amplitude (0.63–0.87V), and industrial temperature operation (−40°C to +85°C).

Technical Context

The PI6LC48H04LIE integrates a proprietary Phase-Locked Loop (PLL) architecture optimized for PCIe 4.0 jitter requirements, featuring selectable loop bandwidths (2–4MHz or 2–5MHz) and CDR reference at 10MHz. Its PLL achieves sub-0.5ps RMS phase jitter across all supported output frequencies when driven by a 25MHz ±30ppm crystal.

It supports flexible output control via two hierarchical enable pins (OE for global enable and OE0&1 for Q0/Q1 subset), tri-level VSWING_CTRL for HCSL swing tuning, and S[1:0] binary-selectable output frequencies-all implemented with internal 343kΩ pull-up resistors on control inputs, eliminating external biasing components.

Key Specifications

Pinout & Package

Package: 20-pin Thin Shrink Small Outline Package (TSSOP), 173 mil width, exposed pad not present, RoHS-compliant lead-free finish.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with IDT8T49N242A and Si5332A-D-GM, the PI6LC48H04LIE offers PCIe 4.0–specific jitter performance at lower cost and simpler configuration, while retaining industrial temperature range and dual-supply flexibility absent in the Si5332A.

Availability

PI6LC48H04LIE is available at Aetrix Electronics and suitable for PCIe 4.0 switch designs, 10/25GbE PHY timing, and industrial network processor boards requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PI6LC48H04LIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for industrial, computing, and communications markets.

The PI6LC48H04LIE belongs to Diodes' Pericom-branded clock generation portfolio, engineered specifically for PCIe 4.0 and multi-gigabit Ethernet timing compliance with minimal external components and industrial reliability.

FAQ

Does the PI6LC48H04LIE support LVDS outputs directly?

No, it provides Low-Power HCSL outputs compatible with LVDS receivers when terminated correctly. The device drives 100Ω differential loads with 0.7V swing (default), matching LVDS common-mode voltage (1.2V) via external resistor networks per the datasheet's LVDS driving diagram (page 8). No internal LVDS driver is present.

What crystal specifications are mandatory for PCIe 4.0 compliance?

A 25MHz fundamental-mode parallel-resonant crystal with ±30ppm stability over −40°C to +85°C and 18pF load capacitance is required. Recommended part numbers include FL2500038 (±20ppm) and FY2500107 (±30ppm). Crystal drive level must stay below 100μW to avoid aging or instability.

How does VSWING_CTRL affect system-level signal integrity?

VSWING_CTRL adjusts HCSL output amplitude to 0.63V, 0.75V (default), or 0.87V, enabling optimization for trace loss, receiver sensitivity, and crosstalk margin. Lower swing reduces EMI and power; higher swing improves noise immunity on long traces-verified by measured 25ps inter-output skew at crossing point across all settings.

Can OE and OE0&1 be used simultaneously for partial power gating?

Yes. OE controls all four outputs globally; OE0&1 controls only Q0± and Q1±. When OE=HIGH and OE0&1=LOW, Q0±/Q1± enter high-Z while Q2±/Q3± remain active-enabling dynamic power reduction in multi-lane systems where only some lanes are active, with 10µs enable/disable timing guaranteed.