Diodes Incorporated PI6LC48L0201LIE

Overview

PI6LC48L0201LIE from Pericom is a 2-output LVDS clock synthesizer optimized for Ethernet reference clock generation, featuring selectable crystal or LVCMOS/LVTTL input, 3.3V/2.5V dual supply support, and ultra-low RMS phase jitter of 0.2ps (156.25MHz, 1.875MHz–20MHz) using a 25MHz crystal. It delivers 62.5MHz, 125MHz, or 156.25MHz outputs via N_SEL[1:0] pins and targets high-integrity timing in networking interfaces.

For engineers reviewing the PI6LC48L0201LIE datasheet, PI6LC48L0201LIE pinout, PI6LC48L0201LIE application, or PI6LC48L0201LIE equivalent, key selection criteria include LVDS output compliance, PLL bypass capability, frequency select pin logic, industrial temperature range (−40°C to +85°C), and separate VDD/VDDA/VDDO power domains for jitter optimization.

Technical Context

The PI6LC48L0201LIE implements a proprietary low-phase-noise PLL architecture with programmable feedback dividers (N_SEL[1:0]) to generate three standard Ethernet frequencies from a 25MHz fundamental-mode crystal. Its analog PLL core (VDDA-supplied) is isolated from digital I/O (VDDO) and core logic (VDD) to minimize supply-induced jitter.

It supports dual input modes: crystal oscillator (XTAL_IN/XTAL_OUT) or single-ended LVCMOS/LVTTL reference (Ref_IN), selected by IN_SEL. Output enable/reset is controlled via M_reset, while PLL_ByPass allows direct pass-through of input clock when PLL is disabled - enabling deterministic startup and test modes.

Key Specifications

Pinout & Package

Package: 20-pin TSSOP (173 mil wide), Pb-free & RoHS-compliant (per PI6LC48L0201LIE ordering code).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS clock synthesizer applications.

Compared with IDT8T49N242BILF and Si5338A-B-GM, the PI6LC48L0201LIE offers the lowest jitter (0.2ps), hardware-selectable frequencies without software, and native crystal interface - making it optimal for cost-sensitive, high-reliability Ethernet PHY timing where simplicity and jitter margin are critical.

Availability

PI6LC48L0201LIE is available at Aetrix Electronics and suitable for 10GBASE-T Ethernet PHY reference clocking, SGMII interface timing, and industrial Ethernet gateway applications requiring stable component supply, long-term lifecycle assurance, and industrial-temperature qualification.

Supply support for PI6LC48L0201LIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance clock generation, signal integrity, and interface solutions for networking, computing, and communications markets.

The PI6LC48L0201LIE belongs to Pericom's HiFlex family - engineered specifically for low-jitter, multi-frequency Ethernet clock synthesis with minimal external components and robust industrial operation.

FAQ

What is the minimum recommended crystal ESR for stable operation?

The datasheet specifies a maximum equivalent series resistance (ESR) of 50Ω for reliable start-up and low-jitter operation with a 25MHz fundamental-mode crystal. Crystals exceeding this value may exhibit marginal oscillation or increased phase noise, especially at temperature extremes. Pericom recommends FL2500047 (25MHz, 18pF CL, ±20ppm) or FY2500091 (25MHz, 18pF CL, ±30ppm) as validated options.

Can the PI6LC48L0201LIE operate with a 12.5MHz crystal?

No - the device is characterized and guaranteed only with 25MHz crystals. The internal PLL architecture and frequency multiplication ratios (N=6.25, 5, 2.5) are optimized for 25MHz input; using 12.5MHz would result in out-of-spec output frequencies and degraded jitter performance due to insufficient VCO tuning range and loop stability margins.

Is PLL bypass mode functional with the crystal input enabled?

Yes - when IN_SEL = 0 (crystal mode) and PLL_ByPass = 1, the crystal oscillator output is routed directly to both LVDS output banks without PLL processing. This provides a low-latency, jitter-pass-through path ideal for system-level validation or fail-safe clocking, though output jitter equals that of the crystal itself (typically >1ps RMS).

How should unused LVDS outputs be terminated?

Unused LVDS output pairs (e.g., CLK1/CLK1# when only CLK0/CLK0# is used) must be either terminated with a 100Ω resistor across the differential pair at the device pin or left floating with no PCB trace attached. Floating outputs with stub traces cause impedance discontinuities and radiated emissions; unterminated floating pins are acceptable only if physically disconnected from routing.