Diodes Incorporated PI6LC48L0201LIEX

Overview

PI6LC48L0201LIEX from Pericom is a 2-output LVDS clock synthesizer optimized for Ethernet reference clock generation, using a 25MHz crystal and two frequency-select pins to deliver 62.5MHz, 125MHz, or 156.25MHz outputs. It employs proprietary low-phase-noise PLL architecture, achieves 0.2ps RMS phase jitter (1.875MHz–20MHz band at 156.25MHz), and supports dual supply modes (3.3V/2.5V) in industrial-temperature operation.

For engineers reviewing the PI6LC48L0201LIEX datasheet, PI6LC48L0201LIEX pinout, PI6LC48L0201LIEX application, or PI6LC48L0201LIEX equivalent, key selection criteria include LVDS output compliance, selectable crystal/LVCMOS input interface, frequency select logic mapping, industrial-grade thermal performance (−40°C to +85°C), and TSSOP-20 package compatibility with Ethernet PHY timing requirements.

Technical Context

The PI6LC48L0201LIEX integrates a fully integrated PLL-based frequency synthesizer with independent analog (VDDA), core (VDD), and output (VDDO) power domains to isolate switching noise and preserve jitter performance. Its PFD/VCO architecture accepts either a parallel-resonant 25MHz crystal (via XTAL_IN/XTAL_OUT) or single-ended LVCMOS reference clock (via Ref_IN), selected by IN_SEL.

Frequency selection is implemented via N_SEL[1:0] pins, enabling three fixed output frequencies without external programming. The device provides two matched LVDS differential output pairs (CLK0/CLK0#, CLK1/CLK1#) with 48–52% duty cycle, <50ps inter-pair skew, and guaranteed DC characteristics across both 3.3V and 2.5V supply configurations.

Key Specifications

Pinout & Package

Package: 20-pin TSSOP (173 mil width), lead-free and RoHS-compliant, with exposed thermal pad not connected internally.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS clock synthesizer applications.

Compared with ICS8430I-01LG and Si5338A-D-GM, the PI6LC48L0201LIEX delivers dual-LVDS outputs with zero-config frequency selection and lowest jitter in its class, making it optimal for cost-sensitive, high-volume Ethernet PHY timing where simplicity and jitter margin are critical.

Availability

PI6LC48L0201LIEX is available at Aetrix Electronics and suitable for 10GBASE-T switch design, industrial Ethernet controller timing, backplane clock distribution, and optical transport network line card synchronization requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PI6LC48L0201LIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, signal integrity, and interface solutions for networking, computing, and communications markets.

The PI6LC48L0201LIEX belongs to Pericom's HiFlex family-designed specifically for low-jitter, multi-output Ethernet clock generation with minimal external components and industrial-grade reliability.

FAQ

What is the minimum recommended crystal ESR for stable operation?

The datasheet specifies a maximum equivalent series resistance (ESR) of 50Ω for reliable oscillation with the PI6LC48L0201LIEX. Crystals exceeding this value may cause start-up failure or increased phase noise. Pericom recommends FL2500047 (25MHz, 18pF, ±20ppm) or FY2500091 (25MHz, 18pF, ±30ppm), both rated at ≤40Ω ESR and validated for this device.

Can the device operate with a 1.8V supply?

No. The PI6LC48L0201LIEX supports only 2.5V and 3.3V supply modes across VDD, VDDA, and VDDO. Operation below 2.375V (min for 2.5V mode) violates absolute maximum ratings and will result in undefined behavior, including PLL unlock or output failure. No 1.8V operation is specified or characterized.

How should unused LVDS outputs be terminated?

Unused LVDS output pairs (e.g., CLK1/CLK1# when only CLK0/CLK0# is used) must be either terminated with a 100Ω resistor across the pair or left floating with no PCB trace attached. Floating outputs with stub traces induce reflections and degrade jitter; unterminated but routed outputs violate LVDS common-mode voltage specifications and risk latch-up.

Is the PLL_ByPass function synchronous or asynchronous?

The PLL_ByPass function is asynchronous: asserting PLL_ByPass = 1 immediately routes the selected reference input (crystal or Ref_IN) directly to both LVDS outputs without waiting for PLL lock state. This enables instantaneous failover during reference loss, but introduces potential glitching if the bypassed signal has duty cycle or edge-rate violations outside LVDS specs.