Diodes Incorporated PI6LC48P0101LIE

Overview

PI6LC48P0101LIE from Diodes Incorporated (acquired Pericom) is a HiFlex 10GbE clock generator IC with one differential LVPECL output, crystal oscillator interface for 18pF parallel resonant crystals (23.2–30 MHz), 312.5 MHz / 625 MHz selectable output frequencies, <0.5 ps RMS phase jitter (12 kHz–20 MHz), and dual-supply operation at 3.3 V or 2.5 V. It serves as the primary timing source in 10 Gigabit Ethernet line cards.

For engineers reviewing the PI6LC48P0101LIE datasheet, PI6LC48P0101LIE pinout, PI6LC48P0101LIE application, or PI6LC48P0101LIE equivalent, key selection criteria include LVPECL output compliance, crystal-based jitter performance below 0.5 ps, FREQ_SEL-controlled frequency doubling, TSSOP-8 footprint constraints, and dual-voltage supply flexibility for system-level power domain alignment.

Technical Context

The PI6LC48P0101LIE integrates a PLL with a fixed M/N ratio (25/1 or 25/2) driven by an external 25 MHz crystal, enabling precise 312.5 MHz or 625 MHz outputs for IEEE 802.3ae 10GbE physical layer timing. Its analog and core supplies (VDDA/VDD) are separated to isolate PLL noise from output drivers.

It accepts either a parallel-resonant crystal (23.2–30 MHz, 18 pF load) or single-ended LVCMOS reference via XTAL_IN/REF_IN, with internal 51 kΩ pulldown on FREQ_SEL. Output duty cycle is tightly controlled at 47–53%, and rise/fall times are specified at 100–400 ps (20–80%).

Key Specifications

Pinout & Package

PI6LC48P0101LIE is housed in an 8-pin, 173-mil wide Pb-free Green TSSOP (Package Code L), optimized for high-density 10GbE PCB layouts with minimal board area and thermal resistance (θ_JA = 124°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with IDT8T49N242BGI and Si5338A-D-GM, PI6LC48P0101LIE offers optimal balance of jitter performance, dual-frequency flexibility, crystal-based simplicity, and TSSOP-8 footprint-making it the most direct fit for cost- and space-constrained 10GbE line card designs requiring 312.5/625 MHz outputs.

Availability

PI6LC48P0101LIE is available at Aetrix Electronics and suitable for 10GbE line cards, optical transport modules, network interface controllers, and carrier-grade routers requiring stable component supply and industrial-temperature timing performance.

Supply support for PI6LC48P0101LIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated acquired Pericom Semiconductor in 2017 and integrates its high-performance timing portfolio into broad analog and mixed-signal solutions for communications and computing markets.

The PI6LC48P0101LIE belongs to Pericom's HiFlex clock generator family, engineered specifically for low-jitter, crystal-referenced timing in 10 Gigabit Ethernet infrastructure equipment.

FAQ

What crystal specifications are mandatory for stable operation?

The PI6LC48P0101LIE requires an 18 pF parallel-resonant fundamental-mode crystal with frequency between 23.2 MHz and 30 MHz, ESR ≤40 Ω, and shunt capacitance ≤7 pF. A 25 MHz crystal is recommended for 10GbE applications. Deviations outside these limits risk startup failure or increased jitter beyond 0.5 ps.

Can the XTAL_IN pin accept a CMOS clock instead of a crystal?

Yes - XTAL_IN functions as a single-ended LVCMOS/LVTTL reference input when driven externally. An AC coupling capacitor is required, and signal amplitude should be reduced to half-swing to prevent rail interference. XTAL_OUT must be left floating in this configuration, and crystal-related components (C1/C2) are omitted.

How does FREQ_SEL determine output frequency?

FREQ_SEL is a logic input with internal 51 kΩ pulldown. When held low (default), it selects M/N = 25/1 → 312.5 MHz output from a 25 MHz crystal. When driven high, it selects M/N = 25/2 → 625 MHz. No external pull-up is needed; a simple GPIO or strap resistor suffices.

Why are separate VDD and VDDA supplies required?

VDD powers digital logic and dividers; VDDA powers the PLL's VCO and phase detector. Separating them prevents digital switching noise from modulating the VCO, which would increase phase jitter. Layout mandates individual vias to power planes and distinct bypassing: 0.1 μF for VDD, and 0.1 μF + 10 Ω + 10 μF for VDDA.