Diodes Incorporated PI6LC48P0101LIEX

Overview

PI6LC48P0101LIEX from Pericom is a 2-output LVDS clock generator optimized for Ethernet reference clock synthesis, featuring dual differential LVDS outputs, selectable crystal or LVCMOS/LVTTL input, and support for 62.5 MHz, 125 MHz, and 156.25 MHz output frequencies using a 25 MHz crystal. It employs proprietary low-phase-noise PLL architecture to achieve 0.2 ps (typical) RMS phase jitter at 156.25 MHz (1.875 MHz–20 MHz offset), operating across 2.5 V or 3.3 V supply rails in industrial temperature range (−40°C to +85°C).

For engineers reviewing the PI6LC48P0101LIEX datasheet, PI6LC48P0101LIEX pinout, PI6LC48P0101LIEX application, or PI6LC48P0101LIEX equivalent, key selection criteria include LVDS output compliance, frequency select pin logic (N_SEL[1:0]), PLL bypass capability via PLL_ByPass pin, and separate analog (VDDA), core (VDD), and output (VDDO) power domains for jitter-sensitive clock distribution in networking PHY interfaces.

Technical Context

The device integrates a fully integrated PLL with programmable feedback divider (N) and reference divider (M), enabling precise synthesis of Ethernet-standard frequencies from a 25 MHz fundamental-mode crystal. Its dual LVDS output banks (CLK0/CLK0#, CLK1/CLK1#) are independently buffered and share no internal coupling path, minimizing inter-channel skew (≤50 ps).

Input flexibility is implemented via IN_SEL pin: logic low selects XTAL_IN/XTAL_OUT crystal interface with internal oscillator circuitry; logic high enables single-ended LVCMOS/LVTTL reference clock injection at Ref_IN. Frequency selection is determined by N_SEL[1:0] pins per documented table, with reserved state (11) undefined.

Key Specifications

Pinout & Package

PI6LC48P0101LIEX is housed in a 20-pin Thin Shrink Small Outline Package (TSSOP-L), 173 mil wide, with 0.65 mm pitch and exposed pad not present. Pin functions are validated per Pericom Rev. A datasheet (07/23/2013) and confirmed on official distributor pages (Digi-Key, Mouser).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS clock generator applications.

Compared with IDT8T49N242A and Si5338A-B-GM, PI6LC48P0101LIEX offers immediate pin-strapped Ethernet frequency selection without configuration overhead or crystal integration trade-offs, making it optimal for cost-sensitive, high-volume 10/100/1000BASE-T designs where jitter and simplicity are prioritized over programmability.

Availability

PI6LC48P0101LIEX is available at Aetrix Electronics and suitable for 10GBASE-T Ethernet PHY clocking, industrial switch fabric timing, and 5G fronthaul reference generation requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for PI6LC48P0101LIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance clock management, signal integrity, and interface solutions for networking, computing, and communications infrastructure.

PI6LC48P0101LIEX belongs to the HiFlex family of low-jitter clock generators, designed specifically to replace discrete crystal oscillators and fanout buffers in Ethernet and telecom timing applications with integrated, pin-configurable solutions.

FAQ

What crystal specifications are required for optimal 156.25 MHz output?

The PI6LC48P0101LIEX is characterized for use with 25 MHz, 18 pF parallel-resonant crystals having ESR ≤50 Ω and shunt capacitance ≈7 pF. Pericom recommends FL2500047 (3.2×2.5 mm, ±20 ppm) or FY2500091 (5×3.2 mm, ±30 ppm). Load capacitors C1/C2 must be 22 pF each to minimize ppm error and maintain phase jitter below 0.2 ps RMS.

Can the device operate with only one LVDS output enabled?

Yes - unused LVDS output pairs (e.g., CLK1/CLK1#) may be left floating or terminated with a 100 Ω differential resistor across the pair. No internal disable function exists, but floating outputs draw negligible current and do not affect jitter performance of the active bank due to physical isolation of output drivers and power domains.

How does the PLL bypass mode affect timing behavior?

When PLL_ByPass = high, the device routes the selected input (crystal or Ref_IN) directly to both LVDS outputs without PLL multiplication or filtering. Output frequency equals input frequency, phase jitter reflects the source's native noise floor (not the 0.2 ps spec), and frequency select pins are ignored - useful for validation or fallback timing paths.

Is separate decoupling required for VDDA, VDD, and VDDO?

Yes - each supply rail requires dedicated 0.1 µF ceramic decoupling placed within 2 mm of its pin. VDDA additionally requires a 10 Ω resistor in series with a 10 µF tantalum capacitor to suppress analog-domain noise. This three-rail decoupling scheme is mandatory to achieve specified sub-0.3 ps RMS jitter and is explicitly called out in Pericom's application note AN-13-0115.