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Diodes Incorporated PI6LC48P02LIE
- Part No.:
- PI6LC48P02LIE
- Manufacturer:
- Diodes Incorporated
- Category:
- Application Specific Clock/Timing
- Package:
- 20-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
PI6LC48P02LIE.pdf
- Description:
- IC FREQ SYNTHESIZER 20TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:4,336
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Product details
Overview
PI6LC48P02LIE from Pericom is a 2-output LVPECL clock generator optimized for Fibre Channel (53.125–212.5 MHz) and Ethernet (50–200 MHz) reference clock synthesis, featuring ultra-low RMS phase jitter (0.28 ps @ 212.5 MHz), dual independent differential outputs, and selectable crystal or LVCMOS reference input - deployed in high-speed networking switches and Fibre Channel HBAs.
For engineers reviewing the PI6LC48P02LIE datasheet, PI6LC48P02LIE pinout, PI6LC48P02LIE application, or PI6LC48P02LIE equivalent, key selection criteria include LVPECL output compliance, multi-frequency crystal-selectable operation, industrial temperature support (−40°C to +85°C), supply flexibility (2.5 V/3.3 V), and 20-pin TSSOP package compatibility with dense PCB layouts.
Technical Context
The PI6LC48P02LIE integrates a proprietary low-phase-noise PLL with programmable N-divider and M-reset control, enabling precise frequency synthesis from 25 MHz, 26.041667 MHz, or 26.5625 MHz crystals. Its dual LVPECL output banks (CLK0/CLK0#, CLK1/CLK1#) operate independently with matched skew ≤30 ps and duty cycle 48–52%.
Frequency selection is implemented via two pull-down N_SEL pins and IN_SEL pin to choose between crystal oscillator or single-ended LVCMOS reference input. The device uses three isolated power domains (VDD core, VDDA analog, VDDO output) to minimize supply-induced jitter - critical for 10G/FC-16 timing integrity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Type | Dual LVPECL differential pairs (CLK0/CLK0#, CLK1/CLK1#) - requires 150 Ω source-to-GND termination per pair |
| RMS Phase Jitter | 0.28 ps @ 212.5 MHz (12 kHz–20 MHz offset) - meets Fibre Channel FC-16 jitter budget |
| Supply Voltage | 2.5 V or 3.3 V (±10%) - supports mixed-voltage system integration without level shifters |
| Operating Temp | −40°C to +85°C - qualified for industrial-grade networking equipment deployment |
| Crystal Support | 25 MHz, 26.041667 MHz, or 26.5625 MHz fundamental-mode crystals - enables exact FC/Ethernet standard frequencies |
| Output Skew | ≤30 ps between CLK0/CLK0# and CLK1/CLK1# - ensures synchronous sampling across multiple PHY lanes |
| Duty Cycle | 48–52% - maintains optimal eye opening for high-speed serial receivers |
Pinout & Package
Package: 20-pin Pb-free TSSOP (173 mil width), JEDEC MO-153F/AC compliant, thermal resistance θJA = 84.0°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 2, 20 | VDDO | Independent 2.5/3.3 V supply for LVPECL output drivers - isolates switching noise from PLL core |
| 3, 4 | CLK0, CLK0# | Differential LVPECL output pair 0 - terminated with 150 Ω to GND and 100 Ω across pins |
| 5 | M_reset | Active-high master reset - forces CLKx low / CLKx# high when asserted; internal 51 kΩ pull-down |
| 6 | PLL_ByPass | PLL enable/bypass control - "0" enables PLL synthesis; "1" passes Ref_IN directly to outputs |
| 8 | VDDA | Analog supply for PLL/VCO - requires 10 Ω + 10 µF RC filter for jitter optimization |
| 9, 11 | N_SEL0, N_SEL1 | 2-bit frequency select inputs - set output frequency based on crystal and lookup table (e.g., 00 → 212.5 MHz w/ 26.5625 MHz Xtal) |
| 12, 13 | XIN, XOUT | Crystal oscillator interface - supports parallel-resonant 18 pF crystals with ESR ≤50 Ω |
| 14 | Ref_IN | LVCMOS/LVTTL single-ended reference input - AC-coupled; amplitude reduced to half-swing to avoid rail interference |
| 15 | IN_SEL | Input source selector - "0" enables crystal; "1" enables Ref_IN; internal pull-down |
| 17 | GND | Analog/digital ground reference - must be connected to low-impedance ground plane |
| 18, 19 | CLK1#, CLK1 | Differential LVPECL output pair 1 - electrically identical to CLK0/CLK0#; independent frequency control |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low phase jitter | 0.28 ps RMS @ 212.5 MHz - enables reliable 10.5 Gbps Fibre Channel link margin |
| Dual independent LVPECL outputs | Two fully buffered differential clocks with <30 ps inter-pair skew - supports dual-port PHY or redundant timing paths |
| Flexible reference input | Selectable crystal oscillator or LVCMOS clock input - simplifies board-level clock tree architecture |
| Multi-voltage operation | 2.5 V or 3.3 V supply modes - interoperable with both legacy and modern ASIC I/O voltage domains |
| Industrial temperature range | −40°C to +85°C operation - validated for uncontrolled data center rack environments |
Applications
| Fibre Channel HBA Timing | 10GbE Switch Reference Clock |
|---|---|
|
Use Scenario: High-density Fibre Channel host bus adapter requiring synchronized 106.25 MHz or 212.5 MHz reference clocks for FC-16 transceivers. IC Role / Device Role / Timing Role: Primary clock synthesizer generating two phase-aligned LVPECL clocks for transmit and receive PHYs. Use Value: Sub-0.3 ps jitter ensures BER <10−12 at 10.5 Gbps; dual outputs eliminate need for external fanout buffer. |
Use Scenario: Layer-2 Ethernet switch ASIC needing 156.25 MHz and 100 MHz reference clocks for SFP+ and management interfaces. IC Role / Device Role / Timing Role: Dual-frequency clock generator supporting both data path (156.25 MHz) and control domain (100 MHz) timing. Use Value: Single-device solution reduces BOM count and layout area vs. discrete oscillators + dividers. |
| Storage Area Network Controller | Data Center Server Baseboard Clock |
|
Use Scenario: SAS/SATA controller card requiring 150 MHz and 200 MHz clocks for PCIe Gen3 x8 and NVMe storage interfaces. IC Role / Device Role / Timing Role: High-stability clock source meeting PCIe Gen3 jitter spec (1.0 ps RMS max) via 0.31 ps measured performance. Use Value: Crystal-based synthesis avoids PLL drift over temperature; 20-TSSOP footprint fits tight controller card spacing. |
Use Scenario: Dual-socket server motherboard needing redundant 100 MHz base clocks for PCH and BMC domains. IC Role / Device Role / Timing Role: Primary system clock generator with M_reset and PLL bypass for fail-safe clock management during boot/firmware update. Use Value: Independent VDDO/VDDA supplies prevent CPU switching noise from degrading BMC timing integrity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IDT8T49N242BILF | 4-output LVDS/LVPECL; integrated EEPROM for custom frequency programming; higher current draw (135 mA) | Supports non-standard frequencies via I²C configuration; not crystal-selectable by pin strapping | Choose for programmable multi-frequency systems where crystal inventory reduction is prioritized over pin-strapped simplicity |
| Si5338A-B-GM | 4-output any-frequency synthesizer; fractional-N PLL; 0.23 ps jitter @ 156.25 MHz; QFN-24 package | Requires external crystal + configuration via I²C; no native pin-strapped FC/Ethernet presets | Choose when >2 outputs or sub-100 kHz offset phase noise matters more than drop-in replacement for FC-16 designs |
Compared with IDT8T49N242BILF and Si5338A-B-GM, the PI6LC48P02LIE offers simpler pin-strapped FC/Ethernet frequency selection, lower power (110 mA), and direct TSSOP compatibility - ideal for cost-sensitive, high-volume FC/HBA designs where fixed-frequency stability outweighs programmability.
Availability
PI6LC48P02LIE is available at Aetrix Electronics and suitable for Fibre Channel HBA design, 10GbE switch development, and storage controller qualification requiring stable component supply across extended production cycles.
Supply support for PI6LC48P02LIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Pericom Semiconductor (acquired by Diodes Incorporated in 2017) specialized in high-performance clock management, signal integrity, and interface solutions for networking and data center applications.
The PI6LC48P02LIE belongs to Pericom's HiFlex family - engineered specifically for low-jitter, multi-standard clock generation in Fibre Channel, Ethernet, and storage systems where deterministic timing is non-negotiable.
FAQ
What crystal specifications are required for guaranteed 212.5 MHz output?
The PI6LC48P02LIE requires a 26.5625 MHz fundamental-mode parallel-resonant crystal with 18 pF load capacitance, ESR ≤50 Ω, and shunt capacitance ≤7 pF. Pericom recommends FL2650003 (3.2×2.5 mm, ±25 ppm) or FY2650002 (5×3.2 mm, ±30 ppm). Deviations beyond these specs may cause frequency error >±50 ppm or startup failure.
Can the PI6LC48P02LIE generate 125 MHz for SGMII applications?
No - the PI6LC48P02LIE does not support 125 MHz output. Its factory-programmed frequency table covers only FC (53.125/106.25/159.375/187.5/212.5 MHz) and Ethernet (50/100/150/156.25/200 MHz) standards. 125 MHz is not listed in any crystal/N_SEL combination in the datasheet's Output Frequency Selection Table.
How is LVPECL output termination implemented on the PCB?
Each LVPECL output pair (e.g., CLK0/CLK0#) must be terminated with a 150 Ω resistor from each pin to GND, plus a 100 Ω resistor across the differential pair. AC coupling via 0.01 µF capacitors to 50 Ω transmission lines is required for measurement; DC-coupled loads must match this termination network to maintain common-mode voltage and signal integrity.
Does the device support spread-spectrum clocking (SSC)?
No - the PI6LC48P02LIE lacks SSC modulation capability. Its PLL is optimized for fixed-frequency, ultra-low-jitter operation. Spread-spectrum features are absent from the block diagram, pinout (no modulation input), and all electrical specifications. For EMI reduction, external SSC-capable clock generators or spread-spectrum oscillators must be used instead.
PI6LC48P02LIE Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Diodes Incorporated
- Series:
- HiFlex™
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- Yes
- Main Purpose:
- Ethernet, Fibre Channel
- Input:
- LVCMOS, LVTTL, Crystal
- Output:
- LVPECL
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 2:2
- Differential - Input:Output:
- No/Yes
- Frequency - Max:
- 226.67MHz
- Voltage - Supply:
- 2.97V ~ 3.63V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-TSSOP
PI6LC48P02LIE FAQ
1.How can I place an order for PI6LC48P02LIE through Aetrix?
Please submit a Request for Quotation (RFQ) for PI6LC48P02LIE on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PI6LC48P02LIE reliable?
The price and inventory of PI6LC48P02LIE are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PI6LC48P02LIE is usually 5 days.
3.What payment methods are accepted for PI6LC48P02LIE?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PI6LC48P02LIE transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PI6LC48P02LIE?
PI6LC48P02LIE orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PI6LC48P02LIE order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PI6LC48P02LIE?
For technical support, including PI6LC48P02LIE datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PI6LC48P02LIE requirements.
6.How does Aetrix verify that PI6LC48P02LIE is sourced from the original manufacturer or authorized distributors?
All PI6LC48P02LIE products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PI6LC48P02LIE meets industry standards.
7.What is the process for return or replacement of PI6LC48P02LIE?
All PI6LC48P02LIE units undergo pre-shipment inspection (PSI). If there is an issue with PI6LC48P02LIE, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PI6LC48P02LIE part is unused and in its original packaging.
Return procedure for PI6LC48P02LIE:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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