Diodes Incorporated PI6LC48P0301AZHE

Overview

PI6LC48P0301AZHE from Pericom is a 3-output LVPECL clock synthesizer optimized for Ethernet reference clock generation, featuring selectable crystal or LVCMOS/LVTTL input, 3.3V/2.5V dual supply support, and ultra-low RMS phase jitter of 0.26ps (typ) at 156.25MHz with 25MHz crystal. It delivers three independent differential LVPECL output pairs (CLKA/CLKA#, CLKB0/CLKB0#, CLKB1/CLKB1#) for multi-rate networking timing in switches, routers, and PHY interfaces.

For engineers reviewing the PI6LC48P0301AZHE datasheet, PI6LC48P0301AZHE pinout, PI6LC48P0301AZHE application, or PI6LC48P0301AZHE equivalent, key selection criteria include LVPECL output skew (≤70ps), bank-selectable divider configuration (NA_SEL/NB_SEL), PLL bypass capability, and compatibility with 25MHz fundamental-mode crystals meeting 19.6–27.2MHz frequency and ≤50Ω ESR specs.

Technical Context

The PI6LC48P0301AZHE implements a proprietary low-phase-noise PLL architecture with programmable feedback and output dividers, enabling precise synthesis of 125MHz, 156.25MHz, 312.5MHz, and 625MHz Ethernet clocks from 25MHz or 32MHz crystals. Its dual-bank LVPECL outputs operate independently with separate power domains (VDDOA/VDDOB) and enable controls (OEA/OEB).

Frequency selection is determined by four-pin logic (FBN, NA_SEL[1:0], NB_SEL[1:0]) and input source selection (IN_SEL#), supporting both crystal oscillator and single-ended reference clock modes. Phase jitter performance is guaranteed across 12kHz–20MHz integration bandwidth, with worst-case RMS jitter capped at 0.4ps for all supported frequencies.

Key Specifications

Pinout & Package

PI6LC48P0301AZHE is housed in a lead-free 28-pin TQFN package (ZH footprint, 4mm × 4mm, 0.5mm pitch) with exposed thermal pad. Power domains are segregated: VDD (core), VDDA (analog PLL), VDDOA/VDDOB (output banks A/B), and multiple GND pins (6 total) for noise isolation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with Si5338A-B-GM and ICS843002AGI-01LFT, the PI6LC48P0301AZHE provides deterministic pin-strapped frequency selection, crystal oscillator integration, and PLL bypass - making it optimal for cost-sensitive, fixed-configuration Ethernet hardware where boot-time clock stability is critical.

Availability

PI6LC48P0301AZHE is available at Aetrix Electronics and suitable for 10GBASE-T switch timing, multi-port 1G/10G router PHY, industrial Ethernet gateway, and optical transport network line card applications requiring stable component supply and guaranteed industrial temperature performance.

Supply support for PI6LC48P0301AZHE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (now part of Diodes Incorporated) specialized in high-performance clock management, interface, and signal integrity solutions for networking, computing, and communications markets.

The PI6LC48P0301AZHE belongs to Pericom's HiFlex™ family of low-jitter clock synthesizers, designed specifically to replace multiple discrete oscillators in Ethernet infrastructure equipment while maintaining strict IEEE 802.3 compliance.

FAQ

What crystal specifications are required for stable operation of PI6LC48P0301AZHE?

The device requires a fundamental-mode parallel-resonant crystal with frequency tolerance matching the selected FBN setting: 19.6–27.2MHz (FBN=0) or 15.313–21.25MHz (FBN=1). Maximum ESR must be ≤50Ω; shunt capacitance should be 7pF; recommended part is FL2500047 (25MHz, 18pF load, ±20ppm). Crystal drive level must not exceed 1mW.

Can PI6LC48P0301AZHE generate different frequencies on each output bank simultaneously?

Yes. Bank A (CLKA/CLKA#) and Bank B (CLKB0/CLKB0#, CLKB1/CLKB1#) operate independently. NA_SEL[1:0] sets CLKA frequency; NB_SEL[1:0] sets both CLKB0 and CLKB1 frequencies. For example, CLKA can run at 625MHz while CLKB0/CLKB1 run at 156.25MHz - verified in Bank A and Bank B frequency tables.

How is LVPECL output termination implemented for PI6LC48P0301AZHE?

Each LVPECL output pair requires source termination: 150Ω resistor from CLKx to GND and 100Ω resistor across CLKx and CLKx#. AC coupling via 0.01µF capacitor to 50Ω transmission line is recommended. Output DC levels are VOH=1.9–2.4V and VOL=1.2–1.6V (3.3V supply), measured at the differential cross-point.

Does PI6LC48P0301AZHE support spread-spectrum clocking (SSC)?

No. The PI6LC48P0301AZHE does not implement spread-spectrum modulation. Its PLL is optimized for ultra-low phase jitter, not EMI reduction. For SSC requirements, designers must use an upstream modulated reference clock applied to Ref_IN, though this will degrade RMS jitter performance beyond datasheet guarantees.