Diodes Incorporated PI6LC48P0301AZHEX

Overview

PI6LC48P0301AZHEX from Pericom is a 3-output LVPECL clock synthesizer optimized for Ethernet reference clock generation, featuring selectable crystal or LVCMOS/LVTTL input, 3.3V/2.5V dual supply support, and ultra-low RMS phase jitter of 0.26ps (typ) at 156.25MHz with 25MHz crystal. It delivers three independent differential outputs-CLKA/CLKA#, CLKB0/CLKB0#, CLKB1/CLKB1#-for multi-port Ethernet PHY timing in switches and routers.

For engineers reviewing the PI6LC48P0301AZHEX datasheet, PI6LC48P0301AZHEX pinout, PI6LC48P0301AZHEX application, or PI6LC48P0301AZHEX equivalent, key selection criteria include LVPECL output skew (≤70ps), bank-selectable frequency dividers (÷1 to ÷8), PLL bypass capability, and 28-pin TQFN package thermal performance (θ_JA = 41.68°C/W).

Technical Context

The PI6LC48P0301AZHEX integrates a proprietary low-phase-noise PLL with programmable feedback and output dividers, enabling precise synthesis of 125MHz, 156.25MHz, 312.5MHz, and 625MHz Ethernet clocks from 25MHz or 32MHz fundamental crystals. Its dual-bank architecture allows independent frequency configuration per output pair via NA_SEL[1:0] and NB_SEL[1:0].

It supports flexible clock source selection through IN_SEL# and offers full 3.3V or 2.5V operation across core (VDD), analog (VDDA), and output banks (VDDOA/VDDOB). Output enable pins (OEA/OEB) and master reset (M_reset) provide deterministic power-up control and dynamic output gating.

Key Specifications

Pinout & Package

Package: 28-pin TQFN (ZH), 5mm × 5mm × 0.8mm, lead-free and RoHS-compliant, with exposed thermal pad for enhanced thermal dissipation (θ_JC = 23.78°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with IDT8T49N242A and Si5332A-D-GM, the PI6LC48P0301AZHEX delivers optimal balance of Ethernet-specific performance, pin-strapped configurability, and dual-voltage support-making it ideal for cost-sensitive, high-volume networking hardware where deterministic jitter and minimal firmware dependency are essential.

Availability

PI6LC48P0301AZHEX is available at Aetrix Electronics and suitable for 10G Ethernet switches, industrial backplanes, OTN line cards, and multi-port routers requiring stable component supply, consistent parametric performance, and long-term lifecycle support.

Supply support for PI6LC48P0301AZHEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, signal integrity, and interface solutions for communications and computing markets.

The PI6LC48P0301AZHEX belongs to Pericom's HiFlex™ family-designed specifically for low-jitter, multi-output Ethernet clock generation with flexible crystal/reference input selection and industrial temperature resilience.

FAQ

What is the minimum recommended crystal load capacitance for PI6LC48P0301AZHEX?

The device is characterized for 18pF parallel-resonant crystals. Recommended part numbers include FL2500047 (25MHz, ±20ppm, 18pF) and FY2500091 (25MHz, ±30ppm, 18pF). Using crystals with CL outside 16–20pF may cause frequency deviation exceeding ±50ppm or startup failure under temperature variation.

Can PI6LC48P0301AZHEX operate with a 20MHz crystal?

Yes-when FBN=0 and NA_SEL[1:0]=01, a 20MHz crystal yields 250MHz output on Bank A. However, this configuration is not IEEE Ethernet-standard; verify system-level timing margins. The datasheet specifies 19.6–27.2MHz as the validated fundamental range for guaranteed performance.

How is output skew measured between CLKA# and CLKB0?

Inter-bank skew (e.g., CLKA# vs. CLKB0) is specified as ≤200ps maximum when outputs run at different frequencies. This measurement is taken at differential cross-points under matched 150Ω-to-GND termination and accounts for propagation delay mismatch between internal divider paths and output driver stages.

Is PLL bypass mode supported for all output banks simultaneously?

No-PLL bypass mode (via PLL_ByPass#) routes the selected clock source (crystal or Ref_IN) directly to all three output banks. It cannot be enabled for one bank while retaining synthesized output on another; the entire device operates in either PLL or bypass mode.