Diodes Incorporated PI6LC48P0301AZHIE

Overview

PI6LC48P0301AZHIE from Pericom is a 3-output LVPECL clock synthesizer optimized for Ethernet reference clock generation, featuring ultra-low phase jitter (0.26ps RMS @156.25MHz), selectable crystal or LVCMOS/LVTTL input, and support for 125/156.25/312.5/625MHz outputs in networking systems.

For engineers reviewing the PI6LC48P0301AZHIE datasheet, PI6LC48P0301AZHIE pinout, PI6LC48P0301AZHIE application, or PI6LC48P0301AZHIE equivalent, key selection criteria include LVPECL output skew (≤70ps), dual supply mode (2.5V/3.3V), industrial temperature range (–40°C to +85°C), and bank-selectable frequency dividers with FBN/NA_SEL/NB_SEL control.

Technical Context

The device integrates a proprietary low-phase-noise PLL with programmable feedback and output dividers, enabling precise synthesis of Ethernet-standard frequencies from 25MHz or 32MHz fundamental crystals. Frequency selection is controlled via four dedicated pins (FBN, NA_SEL[1:0], NB_SEL[1:0]) per output bank.

It supports two independent LVPECL output banks (A and B), each with dedicated enable (OEA/OEB), divider select, and power supplies (VDDOA/VDDOB), allowing asynchronous frequency generation and isolation of switching noise through separate analog (VDDA) and core (VDD) rails.

Key Specifications

Pinout & Package

Package: 28-pin TQFN (ZH), 4mm × 4mm, lead-free and RoHS-compliant, with exposed thermal pad for enhanced thermal dissipation in industrial environments.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with IDT8T49N242A and Si5338A-B-GM, the PI6LC48P0301AZHIE delivers superior jitter performance at 156.25MHz, native dual-voltage operation, and industrial temperature rating-making it optimal for fixed-function, high-reliability Ethernet clocking where simplicity and signal integrity are prioritized over programmability.

Availability

PI6LC48P0301AZHIE is available at Aetrix Electronics and suitable for 10GBASE-T switch PHYs, multi-rate optical transceivers, industrial Ethernet controllers, and NAS SoC designs requiring stable component supply across production lifecycles.

Supply support for PI6LC48P0301AZHIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, interface, and signal-integrity solutions for networking, computing, and communications markets.

The PI6LC48P0301A belongs to Pericom's HiFlex™ family of clock synthesizers, designed specifically to meet stringent jitter and skew requirements of multi-gigabit Ethernet physical layers using low-cost fundamental-mode crystals.

FAQ

What crystal specifications are required for optimal jitter performance?

The PI6LC48P0301AZHIE is characterized for 18pF parallel-resonant fundamental-mode crystals between 19.6MHz and 27.2MHz (FBN=0) or 15.313MHz–21.25MHz (FBN=1). Pericom recommends FL2500047 (25MHz, ±20ppm, 18pF CL) or FY2500091 (25MHz, ±30ppm, 18pF CL) for guaranteed 0.26ps RMS jitter at 156.25MHz.

Can the device operate with a single-ended LVCMOS reference clock instead of a crystal?

Yes. When IN_SEL# is pulled LOW, the Ref_IN pin accepts LVCMOS/LVTTL single-ended input (1.7–3.6V logic levels). The internal circuitry conditions this signal for PLL use, supporting edge rates as slow as 10ns. XTAL_IN and XTAL_OUT may be left floating or terminated with 1kΩ to ground in this configuration.

How are the three LVPECL outputs configured for different frequencies simultaneously?

Bank A (CLKA/CLKA#) and Bank B (CLKB0/CLKB0#, CLKB1/CLKB1#) have independent frequency control: FBN selects feedback divider, NA_SEL[1:0] sets Bank A output divider, NB_SEL[1:0] sets Bank B output divider. This allows concurrent generation of non-harmonic frequencies like 156.25MHz (Bank A) and 125MHz (Bank B) from one 25MHz crystal.

What power supply filtering is required to achieve specified phase jitter?

To achieve 0.26ps RMS jitter, each VDD, VDDA, VDDOA, and VDDOB pin requires individual 0.1µF ceramic bypass capacitors. VDDA additionally needs a 10Ω resistor in series with a 10µF tantalum capacitor to suppress analog supply noise. All supplies must connect directly to the power plane via dedicated vias to prevent shared-impedance coupling.