Diodes Incorporated PI6LC48P0301AZHIEX

Overview

PI6LC48P0301AZHIEX from Pericom is a 3-output LVPECL clock synthesizer optimized for Ethernet reference clock generation, featuring selectable crystal or LVCMOS/LVTTL input, 3.3V/2.5V dual supply support, and ultra-low RMS phase jitter of 0.26ps (typ) at 156.25MHz with 25MHz crystal. It delivers three independent differential LVPECL output pairs (CLKA/CLKA#, CLKB0/CLKB0#, CLKB1/CLKB1#) for multi-bank timing in high-speed networking interfaces.

For engineers reviewing the PI6LC48P0301AZHIEX datasheet, PI6LC48P0301AZHIEX pinout, PI6LC48P0301AZHIEX application, or PI6LC48P0301AZHIEX equivalent, this device supports precise Ethernet frequency synthesis (125/156.25/312.5/625MHz), bank-selectable output dividers, low-skew differential outputs, and industrial-temperature operation - critical for switch/router PHY timing, SFP+ module clocks, and multi-rate SerDes synchronization.

Technical Context

The PI6LC48P0301AZHIEX integrates a proprietary low-phase-noise PLL with programmable feedback and output dividers, enabling deterministic frequency synthesis from 25MHz or 32MHz fundamental crystals. Its dual-bank architecture (Bank A: CLKA pair; Bank B: CLKB0/CLKB1 pairs) allows independent divider configuration via NA_SEL[1:0] and NB_SEL[1:0], supporting mixed-frequency outputs simultaneously.

It supports two clock sources - crystal oscillator (XTAL_IN/XTAL_OUT) or single-ended LVCMOS/LVTTL reference (Ref_IN), selected by IN_SEL#. Power domain separation (VDD, VDDA, VDDO_A, VDDO_B) isolates analog PLL core from digital control and output stages to minimize supply-induced jitter.

Key Specifications

Pinout & Package

PI6LC48P0301AZHIEX is housed in a lead-free 28-pin TQFN (ZH) package with exposed thermal pad. Pin assignment follows JEDEC MO-220 standard, with dedicated power domains (VDD, VDDA, VDDO_A, VDDO_B) and ground pins distributed for optimal noise isolation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with IDT8T49N242A and Si5338A-B-GM, the PI6LC48P0301AZHIEX offers unique crystal/LVCMOS dual-input flexibility, 2.5V/3.3V compatibility, and TQFN-28 compactness - making it optimal for cost-sensitive, space-constrained Ethernet PHY timing where fixed-frequency precision suffices.

Availability

PI6LC48P0301AZHIEX is available at Aetrix Electronics and suitable for 10GBASE-T switch timing, SFP+ module clocking, and industrial Ethernet gateway designs requiring stable component supply, industrial-temperature qualification, and low-phase-jitter performance.

Supply support for PI6LC48P0301AZHIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance clock management, signal integrity, and interface solutions for networking, computing, and communications markets.

The PI6LC48P0301AZHIEX belongs to Pericom's HiFlex™ family - engineered specifically for low-jitter Ethernet reference clock generation with flexible input options and multi-bank LVPECL outputs.

FAQ

What crystal specifications are recommended for optimal jitter performance?

The PI6LC48P0301AZHIEX is characterized with 18pF parallel-resonant fundamental-mode crystals. Pericom recommends FL2500047 (25MHz, SMD 3.2×2.5mm, ±20ppm) or FY2500091 (25MHz, SMD 5×3.2mm, ±30ppm). ESR must be ≤50Ω; shunt capacitance should be 7pF; drive level ≤1mW. Crystal load capacitors C1/C2 = 22pF each minimize ppm error.

Can the device operate with a 2.5V supply only, and what are the implications?

Yes - the PI6LC48P0301AZHIEX supports full functionality at 2.5V across VDD, VDDA, and VDDO rails. LVPECL output voltage levels shift to VOH = 1.1–1.6V and VOL = 0.4–0.8V, maintaining valid differential swing (>0.5V) into 100Ω termination. All AC specs including jitter and skew remain guaranteed per datasheet.

How is output skew managed between Bank A and Bank B outputs?

Bank skew (within same bank) is specified at 25ps max; output skew (between banks) is 70ps max for same-frequency outputs and 200ps max for different frequencies. This is achieved through matched internal routing, separate output power domains, and synchronous divider architectures - critical for multi-lane SerDes alignment.

Is the PLL bypass mode functional with LVCMOS reference input?

Yes - asserting PLL_ByPass# (active-low) disables the PLL and routes Ref_IN directly to output dividers. This mode supports jitter transfer rather than jitter generation, enabling use as a low-skew fanout buffer when driven by a low-jitter master clock, while retaining full divider control via NA_SEL/NB_SEL pins.