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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Diodes Incorporated PI6LC48P0301LEX

Name: PI6LC48P0301LEX
Brand: Diodes Incorporated
SKU: PI6LC48P0301LEX
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: PI6LC48P0301LEX

Manufacturer:: Diodes Incorporated

Category:: Application Specific Clock/Timing

Package:: 24-TSSOP (0.173", 4.40mm Width)

Datasheet:: PI6LC48P0301LEX.pdf

Description:: 3-OUTPUT ETHERNET LVPECL SYNTHES

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Product details

Overview

PI6LC48P0301 from Pericom is a 3-output LVPECL clock synthesizer optimized for Ethernet reference clock generation, featuring ultra-low phase jitter (0.16ps RMS @ 156.25MHz), selectable 25MHz/19.53125MHz crystal or LVCMOS input, and independent Bank A/B output dividers supporting 125/156.25/312.5/625MHz outputs in networking systems.

For engineers reviewing the PI6LC48P0301 datasheet, PI6LC48P0301 pinout, PI6LC48P0301 application, or PI6LC48P0301 equivalent, key selection criteria include differential LVPECL output skew (≤70ps within bank), dual supply mode (2.5V/3.3V), crystal ESR tolerance (≤50Ω), and industrial temperature support (–40°C to +85°C).

Technical Context

The PI6LC48P0301 implements a proprietary low-phase-noise PLL architecture with separate analog (VDDA) and core (VDD) power domains to isolate switching noise from the VCO and PFD. It supports two independent clock banks-Bank A (CLKA/CLKA#) and Bank B (CLKB0/CLKB0#, CLKB1/CLKB1#)-each with dedicated divider control pins (NA_SEL[1:0], NB_SEL[1:0]) and output enables (OEA, OEB).

Frequency selection is determined by crystal frequency (19.44–27.2MHz fundamental), feedback divider (FBN), and output divider settings, enabling precise Ethernet-compliant frequencies including 125MHz, 156.25MHz, 312.5MHz, and 625MHz without external programming. The device operates in either crystal oscillator or single-ended LVCMOS reference input mode via IN_SEL#.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Type	Differential LVPECL with 150Ω source termination to GND and 100Ω across CLK/CLK#
RMS Phase Jitter	0.16ps typical @ 156.25MHz (1.875MHz–20MHz offset)
Supply Voltage	2.5V or 3.3V operation with independent VDD, VDDA, VDDO_A, VDDO_B rails
Output Frequency Range	61.25MHz to 680MHz depending on output divider setting (÷1 to ÷8)
Input Options	19.44–27.2MHz parallel-resonant crystal or LVCMOS/LVTTL single-ended reference
Operating Temperature	–40°C to +85°C ambient, qualified for industrial applications
Package	24-pin Pb-free TSSOP (L), 173mil width, JEDEC MO-153F/AD compliant

Pinout & Package

PI6LC48P0301 is housed in a 24-pin lead-free TSSOP (Package Code L), with pin 1 at top-left corner when notch is oriented upward. Power domains are segregated: VDD (core), VDDA (analog), VDDO_A/VDDO_B (output banks), and GND (pin 14). All control inputs feature internal pull-up/pull-down resistors.

Pin/Terminal	Circuit Role	Design Meaning
1, 24 (NB_SEL0, NB_SEL1)	Bank B output divider select input	Configures CLKB0/CLKB1 output frequency via 2-bit binary code; pull-up default
2 (PLL_ByPass#)	Active-low PLL bypass enable	When asserted, disables PLL and passes reference directly to outputs; pull-up default
3 (M_reset)	Master reset input	Active-high; forces all LVPECL outputs to defined low/high state; pull-down default
4, 23 (VDDOA, VDDOB)	Bank A/B output power supply	Separate 2.5V/3.3V supplies for LVPECL output stages to minimize crosstalk
5, 6 (CLKA, CLKA#)	Bank A differential LVPECL output	Primary high-frequency output pair; supports up to 625MHz with <70ps intra-bank skew
7 (OEB)	Bank B output enable	Active-low; disables CLKB0/CLKB1 outputs by forcing differential low; pull-up default
8 (OEA)	Bank A output enable	Active-low; disables CLKA/CLKA#; pull-up default
9 (FBN)	Feedback divider select	Selects PLL feedback ratio (÷1 or ÷2); pull-down default
10 (VDDA)	Analog power supply	Supplies PLL analog circuitry (VCO, PFD); requires 10Ω + 10µF RC filter per datasheet
11 (VDD)	Core digital power supply	Supplies logic, dividers, and control circuitry; bypassed with 0.1µF capacitor
12, 13 (NA_SEL0, NA_SEL1)	Bank A output divider select	2-bit code sets CLKA/CLKA# frequency; pull-up default
15, 16 (XTAL_OUT, XTAL_IN)	Crystal oscillator interface	Drives and senses parallel-resonant crystal; unused pins may float or be grounded via 1kΩ
17 (Ref_IN)	LVCMOS/LVTTL reference input	Accepts single-ended clock (AC-coupled); disabled when IN_SEL# = HIGH
18 (IN_SEL#)	Input source selector	High = crystal mode; Low = Ref_IN mode; pull-up default
19, 20 (CLKB1#, CLKB1)	Bank B secondary LVPECL output	Independent of CLKB0; supports different frequency/divider settings
21, 22 (CLKB0#, CLKB0)	Bank B primary LVPECL output	Configurable via NB_SEL[1:0]; supports same frequency range as CLKA but independent control

Key Features

Feature	Design Value
Ultra-low phase jitter performance	0.14ps RMS @ 625MHz (1.875MHz–20MHz), enabling IEEE 802.3 compliance for 10GBase-T PHY clocks
Independent dual-output banks	Bank A (CLKA) and Bank B (CLKB0/CLKB1) each have dedicated dividers, enables, and power supplies for isolated timing domains
Flexible input configuration	Supports both crystal (19.44–27.2MHz) and LVCMOS reference inputs, simplifying board-level clock tree design
Industrial-grade thermal design	QJA = 84.0°C/W and QJC = 13.0°C/W ensure stable operation under sustained load in compact networking enclosures
Pb-free and green packaging	24-pin TSSOP (L) meets RoHS and JEDEC MO-153F/AD standards with tape-and-reel option (X suffix)

Applications

10GBase-T Ethernet Switch

Multi-port Gigabit Router

Use Scenario: High-density switch ASIC requiring synchronized 156.25MHz and 312.5MHz reference clocks for SERDES lanes and packet processing units.

IC Role / Device Role / Timing Role: Primary clock synthesizer generating two independent LVPECL outputs-one for PHY interface, one for MAC subsystem-with sub-0.2ps jitter.

Use Value: Eliminates need for multiple discrete oscillators; reduces board area and EMI by integrating dual-frequency synthesis with bank-isolated power domains.

Use Scenario: Carrier-grade router with 24+ SFP+ ports, each needing deterministic 125MHz or 156.25MHz clocks for optical transceivers and traffic management engines.

IC Role / Device Role / Timing Role: Centralized clock generator providing three LVPECL outputs-two for redundant PHY banks and one for control-plane timing-with configurable skew compensation.

Use Value: Enables single-chip clock distribution across heterogeneous port groups while maintaining IEEE 1588 boundary clock jitter requirements.

Network Attached Storage Controller

Industrial Ethernet Gateway

Use Scenario: RAID controller SoC requiring 125MHz PCIe Gen3 reference and 156.25MHz Ethernet MAC clock with tight inter-clock alignment.

IC Role / Device Role / Timing Role: Dual-bank synthesizer delivering CLKA@125MHz and [email protected] with ≤70ps intra-bank skew and ≤200ps inter-bank skew.

Use Value: Ensures deterministic timing margin between storage I/O and network I/O paths, preventing buffer underrun/overrun in real-time streaming workloads.

Use Scenario: DIN-rail mounted gateway connecting legacy fieldbus (PROFINET, EtherCAT) to cloud infrastructure, operating in –40°C to +85°C environments.

IC Role / Device Role / Timing Role: Industrial-qualified clock source generating 125MHz and 625MHz outputs for dual-core ARM processor and multi-gigabit Ethernet PHYs.

Use Value: Guarantees long-term stability and jitter performance over full temperature range without derating, meeting IEC 61000-6-2 EMC immunity requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
IDT8T49N242	4-output LVPECL, integrated crystal oscillator, higher current draw (200mA), no crystal input option	Eliminates external crystal but lacks flexibility for custom reference sources	Choose when board space is constrained and fixed 156.25MHz output suffices
Si5338A-B-GM	4-output programmable Any-Frequency™ synthesizer, CMOS/LVDS/LVPECL configurable, I²C interface required	Requires firmware initialization and external EEPROM; supports non-standard frequencies	Choose when multi-protocol timing (USB, PCIe, SATA) must coexist on same board

Compared with IDT8T49N242 and Si5338A-B-GM, the PI6LC48P0301 offers simpler hardware-only configuration via pin strapping, lower power (150mA max), and direct crystal/LVCMOS input flexibility-making it optimal for cost-sensitive, high-volume Ethernet switch designs where standard frequencies dominate.

Availability

PI6LC48P0301 is available at Aetrix Electronics and suitable for 10GBase-T switches, multi-port routers, and industrial Ethernet gateways requiring stable component supply, industrial temperature qualification, and ultra-low-jitter clock synthesis.

Supply support for PI6LC48P0301 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance clock, interface, and signal integrity solutions for networking, computing, and communications markets.

The PI6LC48P0301 belongs to Pericom's HiFlex family-designed specifically for Ethernet reference clock generation with emphasis on phase noise, output isolation, and pin-strapped configurability in space-constrained networking hardware.

FAQ

What crystal specifications are required for optimal PI6LC48P0301 performance?

The PI6LC48P0301 is characterized for 18pF parallel-resonant crystals with fundamental-mode frequencies between 19.44MHz and 27.2MHz (FBN=0) or 15.313–21.25MHz (FBN=1). Equivalent series resistance must not exceed 50Ω, and drive level should remain ≤1mW. Pericom recommends FL2500047 (25MHz, ±20ppm) or FY2500091 (25MHz, ±30ppm) for production use.

How does the PI6LC48P0301 handle power supply noise sensitivity?

The device uses physically separated power domains-VDD (core logic), VDDA (analog PLL), and VDDO_A/VDDO_B (LVPECL outputs)-to prevent coupling. Each supply requires dedicated 0.1µF ceramic bypassing; VDDA additionally needs a 10Ω resistor in series with a 10µF capacitor to suppress low-frequency ripple that could modulate VCO phase noise.

Can unused LVPECL outputs be left unconnected?

Yes, all unused LVPECL outputs (CLKA, CLKA#, CLKB0, CLKB0#, CLKB1, CLKB1#) may be left floating without termination. However, corresponding output enable pins (OEA, OEB) must be held LOW to disable the drivers and prevent unintended current draw or signal radiation from unterminated lines.

What is the maximum allowable skew between CLKA and CLKB0 outputs?

The datasheet specifies 200ps maximum output skew (tsk(o)) between outputs operating at different frequencies. This value is measured at the differential cross-point under matched load conditions and applies to CLKA vs. CLKB0/CLKB1 when configured for distinct frequencies-critical for multi-domain synchronization in switch fabric designs.

PI6LC48P0301LEX Specifications

Product attributes: Attribute value

Manufacturer:: Diodes Incorporated

Series:: -

Package/Case:: 24-TSSOP (0.173", 4.40mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: Yes with Bypass

Main Purpose:: Ethernet

Input:: LVCMOS, LVTTL, Crystal

Output:: LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 2:3

Differential - Input:Output:: No/Yes

Frequency - Max:: 680MHz

Voltage - Supply:: 2.375V ~ 2.625V, 3.135V ~ 3.465V

Operating Temperature:: -40°C ~ 85°C (TA)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-TSSOP

PI6LC48P0301LEX FAQ

1.How can I place an order for PI6LC48P0301LEX through Aetrix?

Please submit a Request for Quotation (RFQ) for PI6LC48P0301LEX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for PI6LC48P0301LEX reliable?

The price and inventory of PI6LC48P0301LEX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PI6LC48P0301LEX is usually 5 days.

3.What payment methods are accepted for PI6LC48P0301LEX?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PI6LC48P0301LEX transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for PI6LC48P0301LEX?

PI6LC48P0301LEX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your PI6LC48P0301LEX order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for PI6LC48P0301LEX?

For technical support, including PI6LC48P0301LEX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PI6LC48P0301LEX requirements.

6.How does Aetrix verify that PI6LC48P0301LEX is sourced from the original manufacturer or authorized distributors?

All PI6LC48P0301LEX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PI6LC48P0301LEX meets industry standards.

7.What is the process for return or replacement of PI6LC48P0301LEX?

All PI6LC48P0301LEX units undergo pre-shipment inspection (PSI). If there is an issue with PI6LC48P0301LEX, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The PI6LC48P0301LEX part is unused and in its original packaging.

Return procedure for PI6LC48P0301LEX:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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