Diodes Incorporated PI6LC48P0301LIE

Overview

PI6LC48P0301LIE from Pericom is a 3-output LVPECL clock synthesizer optimized for Ethernet reference clock generation, featuring ultra-low phase jitter (0.16ps RMS @156.25MHz), selectable 25MHz or 19.53125MHz crystal input, and dual supply support (2.5V/3.3V). It delivers three independent differential outputs-CLKA/CLKA#, CLKB0/CLKB0#, CLKB1/CLKB1#-and targets high-integrity timing in 1G/10G Ethernet PHY interfaces.

For engineers reviewing the PI6LC48P0301LIE datasheet, PI6LC48P0301LIE pinout, PI6LC48P0301LIE application, or PI6LC48P0301LIE equivalent, key selection criteria include LVPECL output skew (≤70ps bank skew), RMS phase jitter across 125–625MHz, crystal vs. LVCMOS reference input flexibility, and industrial-temperature operation (−40°C to +85°C).

Technical Context

The PI6LC48P0301LIE integrates a proprietary low-phase-noise PLL with programmable feedback and output dividers, enabling precise synthesis of Ethernet-standard frequencies (125MHz, 156.25MHz, 312.5MHz, 625MHz) from fundamental crystals. Its architecture separates analog (VDDA), core (VDD), and output (VDDOA/VDDOB) power domains to suppress switching noise coupling into timing paths.

Frequency selection is implemented via four dedicated control pins (FBN, NA_SEL[1:0], NB_SEL[1:0]) that configure integer feedback and output division ratios. The device supports both crystal oscillator mode (XTAL_IN/XTAL_OUT) and single-ended LVCMOS/LVTTL reference input (Ref_IN), with IN_SEL# determining source selection.

Key Specifications

Pinout & Package

Package: 24-pin TSSOP (lead-free, RoHS-compliant), 173-mil width, JEDEC MO-153F/AD compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with IDT8T49N242A and Si5338A-B-GM, the PI6LC48P0301LIE uniquely combines hardware-based reference selection (crystal/LVCMOS), PLL bypass for failover, and industrial-temperature LVPECL outputs - making it optimal for Ethernet PHY timing where deterministic behavior and minimal firmware dependency are critical.

Availability

PI6LC48P0301LIE is available at Aetrix Electronics and suitable for 10GBASE-T Ethernet PHYs, carrier-grade network switches, and industrial Ethernet controllers requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PI6LC48P0301LIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, interface, and signal integrity solutions for networking, computing, and communications markets.

The PI6LC48P0301LIE belongs to Pericom's HiFlex family of clock synthesizers, engineered specifically for low-jitter Ethernet reference clock generation with emphasis on hardware configurability, noise isolation, and industrial reliability.

FAQ

What crystal specifications are required for optimal 156.25MHz output performance?

The PI6LC48P0301LIE is characterized with 18pF parallel-resonant crystals. For 156.25MHz output using a 25MHz crystal, Pericom recommends FL2500047 (SMD 3.2×2.5mm, ±20ppm) or FY2500091 (SMD 5×3.2mm, ±30ppm). Crystal ESR must be ≤50Ω, shunt capacitance ≤7pF, and drive level ≤1mW to maintain phase jitter below 0.16ps RMS.

How does the PLL bypass mode affect output timing behavior?

When PLL_ByPass# is asserted (LOW), the internal PLL is disabled and Ref_IN is routed directly to all outputs. This eliminates PLL-induced jitter and lock time, but output frequency is limited to the Ref_IN source. The feature enables deterministic clock failover during crystal faults while maintaining sub-100ns phase continuity - critical for hitless Ethernet link recovery.

Can CLKA and CLKB0 operate at different frequencies simultaneously?

Yes. Bank A (CLKA/CLKA#) and Bank B (CLKB0/CLKB0#, CLKB1/CLKB1#) have independent divider controls (NA_SEL[1:0] and NB_SEL[1:0]). For example, CLKA can be set to 156.25MHz while CLKB0 runs at 125MHz using different crystal input configurations and divider settings - supporting multi-rate Ethernet PHYs without external multiplexing.

What is the recommended power supply decoupling strategy for VDDA?

VDDA requires a 10Ω series resistor and 10µF bulk capacitor in addition to the standard 0.1µF ceramic bypass capacitor. This RC filter attenuates high-frequency digital noise coupling from VDD into the analog PLL section. The resistor value scales with supply voltage: for 2.5V operation, use a lower resistance per Pericom Application Note AN-501 to maintain optimal PSRR.