Diodes Incorporated PI6LC48P0301LIEX

Overview

PI6LC48P0301LIEX from Pericom is a 3-output LVPECL clock synthesizer optimized for Ethernet reference clock generation, featuring ultra-low phase jitter (0.16ps RMS @ 156.25MHz), selectable 25MHz/19.53125MHz crystal or LVCMOS input, and dual-bank programmable output dividers supporting 125/156.25/312.5/625MHz outputs in networking systems.

For engineers reviewing the PI6LC48P0301LIEX datasheet, PI6LC48P0301LIEX pinout, PI6LC48P0301LIEX application, or PI6LC48P0301LIEX equivalent, this page delivers verified electrical specs, bank-selectable LVPECL timing architecture, supply voltage flexibility (2.5V/3.3V), and real-world Ethernet clocking use cases with precise jitter and skew data.

Technical Context

The PI6LC48P0301LIEX implements a proprietary low-phase-noise PLL with independent Bank A (CLKA/CLKA#) and Bank B (CLKB0/CLKB0#, CLKB1/CLKB1#) output paths, each controlled by dedicated divider select pins (NA_SEL[1:0], NB_SEL[1:0]) and feedback configuration (FBN). It supports both fundamental-mode crystal oscillation (19.6–27.2MHz) and single-ended LVCMOS reference input via IN_SEL#.

Its triple LVPECL output structure enables simultaneous generation of multiple Ethernet-compliant frequencies-e.g., 125MHz for Gigabit Ethernet PHYs and 156.25MHz for 10GBase-R line interfaces-with bank-level output enable (OEA/OEB) and master reset (M_reset) for deterministic power-up sequencing and dynamic frequency switching.

Key Specifications

Pinout & Package

Package: 24-pin TSSOP (L), Pb-free & Green, 173-mil wide, JEDEC MO-153F/AD compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with IDT8T49N242A and Si5338A-B-GM, the PI6LC48P0301LIEX offers lower phase jitter and simpler GPIO-based configuration-making it optimal for cost-sensitive, high-channel-count Ethernet switches where jitter margin and pin-strapped simplicity are prioritized over programmability.

Availability

PI6LC48P0301LIEX is available at Aetrix Electronics and suitable for Ethernet switch PHY interface, 10GBase-R line card timing, and optical transport network (OTN) timing requiring stable component supply, long-term lifecycle support, and industrial temperature qualification.

Supply support for PI6LC48P0301LIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance clock management, interface, and signal integrity solutions for networking, computing, and communications infrastructure.

The PI6LC48P0301LIEX belongs to Pericom's HiFlex family-designed specifically for low-jitter, multi-output Ethernet clock synthesis with flexible crystal/reference input and industrial-grade reliability.

FAQ

What crystal specifications are required for optimal jitter performance?

The PI6LC48P0301LIEX is characterized for 18pF parallel-resonant crystals operating at 19.53125MHz or 25MHz. Pericom recommends FL2500047 (25MHz, ±20ppm, 3.2×2.5mm) or FY2500091 (25MHz, ±30ppm, 5×3.2mm). ESR must be ≤50Ω, shunt capacitance ≤7pF, and drive level ≤1mW to maintain 0.16ps RMS jitter at 156.25MHz.

Can the device operate with only a single-ended LVCMOS reference input?

Yes-asserting IN_SEL# = LOW selects the Ref_IN pin as the clock source. The input accepts 2.5V or 3.3V LVCMOS/LVTTL signals with edge rates down to 10ns. For best jitter performance, reduce amplitude to half-swing and use AC coupling with a 0.01µF capacitor; unused XTAL_IN/XTAL_OUT pins may be left floating or tied to ground via 1kΩ resistors.

How are the three LVPECL outputs electrically isolated from each other?

The PI6LC48P0301LIEX provides fully independent power domains: VDDOA powers Bank A (CLKA/CLKA#), VDDOB powers Bank B (CLKB0/CLKB0#, CLKB1/CLKB1#), and VDDA supplies the analog PLL core. Each supply requires its own 0.1µF bypass capacitor, and VDDA additionally needs a 10Ω resistor + 10µF capacitor for enhanced analog noise rejection-ensuring <25ps bank-to-bank skew under matched load conditions.

What is the function of the M_reset pin during power-up sequencing?

M_reset is an active-HIGH master reset that forces CLKA/CLKA#, CLKB0/CLKB0#, and CLKB1/CLKB1# into defined differential states: CLKx = LOW, CLKx# = HIGH. This prevents metastability and false clock edges during power ramp-up. It must be held HIGH until VDD, VDDA, and VDDO supplies stabilize (typically >100µs), then driven LOW to enable outputs-ensuring deterministic PLL lock and output activation.