Diodes Incorporated PI6LC48P03AZHIE

Overview

PI6LC48P03AZHIE from Pericom is a 3-output LVPECL clock synthesizer optimized for Ethernet reference clock generation, supporting 125MHz, 156.25MHz, 312.5MHz, and 625MHz outputs via crystal (31.25MHz or 26.041666MHz) or LVCMOS input, with ultra-low 0.3ps RMS phase jitter (12kHz–20MHz) at 156.25MHz, full 3.3V/2.5V supply support, and industrial temperature range (−40°C to +85°C).

For engineers reviewing the PI6LC48P03AZHIE datasheet, PI6LC48P03AZHIE pinout, PI6LC48P03AZHIE application, or PI6LC48P03AZHIE equivalent, key selection criteria include differential LVPECL output skew (≤60ps), bank-selectable output dividers (NA_SEL/NB_SEL), PLL bypass capability, and dual-input mode (crystal or reference clock) for flexible timing architecture integration in networking hardware.

Technical Context

The PI6LC48P03AZHIE implements a proprietary low-phase-noise PLL architecture with separate analog (VDDA), core (VDD), and bank-specific output (VDDOA/VDDOB) power domains to isolate switching noise and preserve jitter performance. It supports two crystal frequencies (31.25MHz and 26.041666MHz) and uses four frequency-select pins (FBN, NA_SEL[1:0], NB_SEL[1:0]) to configure output frequencies across three independent LVPECL banks.

Each output bank (A: CLKA/CLKA#; B: CLKB0/CLKB0#, CLKB1/CLKB1#) features individual enable controls (OEA/OEB), divider select inputs, and pull-up/pull-down internal terminations. The device operates in either crystal oscillator mode (XTAL_IN/XTAL_OUT active) or single-ended reference clock mode (Ref_IN active), selected by IN_SEL#.

Key Specifications

Pinout & Package

Package: 28-pin TQFN (ZH), 4mm × 4mm, 0.5mm pitch, lead-free and RoHS-compliant, with exposed thermal pad for enhanced thermal dissipation (θ_JA = 41.68°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with IDT8T49N242A and Si5338A-D-GM, the PI6LC48P03AZHIE delivers optimal balance of Ethernet-specific frequency support, low jitter, pin-strapped configurability, and compact 28-TQFN packaging - making it ideal for space-constrained, high-volume networking hardware where crystal-based stability and deterministic timing are prioritized over programmability.

Availability

PI6LC48P03AZHIE is available at Aetrix Electronics and suitable for 10GbE switch PHYs, industrial Ethernet controllers, optical transport framer modules, and Gigabit router MAC interfaces requiring stable component supply and guaranteed industrial temperature performance.

Supply support for PI6LC48P03AZHIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, signal integrity, and interface solutions for networking, computing, and communications infrastructure.

The PI6LC48P03AZHIE belongs to Pericom's HiFlex family - engineered specifically for low-jitter, multi-output Ethernet clock generation with flexible crystal/reference input and bank-isolated power domains.

FAQ

What is the recommended termination for the LVPECL outputs?

Each LVPECL output pair requires 150Ω source termination to GND and a 100Ω AC-coupling resistor across CLK and CLK# (per JEDEC standards). A 0.01µF AC-coupling capacitor is mandatory before the 50Ω load. This configuration ensures proper common-mode voltage (≈VDD − 1.3V), minimizes reflections, and maintains <60ps inter-output skew under matched load conditions.

Can the PI6LC48P03AZHIE operate with both 2.5V and 3.3V supplies simultaneously?

Yes - VDD (core), VDDA (analog), and VDDO_A/VDDO_B (output banks) can be independently set to either 2.5V or 3.3V. However, all pins within a supply domain must share the same voltage. For example, VDDA and VDDO_A must match (both 2.5V or both 3.3V), but VDDA may differ from VDD if noise isolation requirements justify split-rail operation.

How is frequency selection implemented without I²C or SPI?

Frequency is set entirely via hardwired logic pins: FBN, NA_SEL[1:0], and NB_SEL[1:0]. These four pins encode binary values that configure internal feedback dividers - e.g., NA_SEL1=1, NA_SEL0=0, FBN=0 with 31.25MHz crystal yields 156.25MHz on Bank A. No serial interface or firmware is needed, enabling zero-latency startup and deterministic behavior.

What happens to outputs during master reset (M_reset = HIGH)?

When M_reset is asserted HIGH, all LVPECL outputs enter a defined high-impedance-like state: CLKA goes low, CLKA# goes high, and similarly for CLKB0/CLKB0# and CLKB1/CLKB1#. This prevents bus contention during power sequencing and ensures clean, glitch-free deassertion before re-enabling outputs via OEA/OEB after reset release.