Diodes Incorporated PI6LC48P03AZHIEX

Overview

PI6LC48P03AZHIEX from Pericom is a 3-output LVPECL clock synthesizer optimized for Ethernet reference clock generation, supporting 125 MHz, 156.25 MHz, 312.5 MHz, and 625 MHz outputs via selectable crystal (31.25 MHz or 26.041666 MHz) or LVCMOS reference input, with ultra-low 0.3 ps RMS phase jitter (12 kHz–20 MHz) at 156.25 MHz, full 3.3 V/2.5 V supply compatibility, and industrial temperature operation (−40°C to +85°C).

For engineers reviewing the PI6LC48P03AZHIEX datasheet, PI6LC48P03AZHIEX pinout, PI6LC48P03AZHIEX application, or PI6LC48P03AZHIEX equivalent, key selection criteria include differential LVPECL output skew (≤60 ps), bank-selectable output dividers (NA_SEL/NB_SEL), PLL bypass capability, and dual-input mode (crystal or single-ended reference) for flexible system clock architecture in high-speed networking hardware.

Technical Context

The PI6LC48P03AZHIEX implements a proprietary low-phase-noise PLL architecture with independent output banks (A and B), each supporting two LVPECL differential pairs (CLKA/CLKA#, CLKB0/CLKB0#, CLKB1/CLKB1#) and configurable feedback division via FBN pin. It supports both fundamental-mode parallel-resonant crystals (18 pF load, 28–35 MHz or 23.33–29.167 MHz) and single-ended LVCMOS/LVTTL reference inputs.

Output frequency selection is determined by three control bits-NA_SEL[1:0], NB_SEL[1:0], and FBN-enabling four discrete output frequencies per bank. The device features separate power domains (VDD, VDDA, VDDOA, VDDOB) to isolate analog PLL core, digital logic, and output drivers, minimizing supply-induced jitter and enabling robust operation in noise-sensitive 10G/25G Ethernet PHY interfaces.

Key Specifications

Pinout & Package

Package: 28-pin TQFN (ZH28), 4 mm × 4 mm × 0.8 mm, Pb-free and RoHS-compliant, with exposed thermal pad.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with IDT8T49N242A and Si5338A-B-GM, the PI6LC48P03AZHIEX offers simpler pin-strapped configuration, lower power (132 mA), dedicated Ethernet frequency support, and hardware-controlled bank enables - making it optimal for cost-sensitive, fixed-function 10G/25G Ethernet hardware without firmware overhead.

Availability

PI6LC48P03AZHIEX is available at Aetrix Electronics and suitable for 10GBASE-KR backplanes, 25G Ethernet PHYs, industrial Ethernet switches, and OTN FEC subsystems requiring stable component supply, consistent lead times, and long-term lifecycle support.

Supply support for PI6LC48P03AZHIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance clock management, signal integrity, and interface solutions for networking, computing, and communications infrastructure.

The PI6LC48P03AZHIEX belongs to Pericom's HiFlex family of low-jitter clock synthesizers, designed specifically to meet IEEE 802.3 Ethernet reference clock specifications with minimal external components and robust industrial operation.

FAQ

What crystal specifications are required for optimal performance?

The PI6LC48P03AZHIEX is characterized for 18 pF parallel-resonant crystals at 31.25 MHz or 26.041666 MHz, with ESR ≤50 Ω, shunt capacitance ≤7 pF, and drive level ≤1 mW. Pericom recommends FY3120001 (31.25 MHz) or FL2600155 (26.041666 MHz). Deviations increase ppm error and degrade phase jitter performance.

Can the device operate with only a single-ended reference clock?

Yes - the Ref_IN pin accepts LVCMOS/LVTTL signals (2 V min HI, 0.8 V max LO at 3.3 V supply). IN_SEL# must be pulled LOW to select this mode. AC-coupling with a 0.01 µF capacitor is recommended, and amplitude should be reduced to half-swing to minimize rail interference and preserve jitter performance.

How is output skew managed between Bank A and Bank B?

Skew between Bank A and Bank B outputs is not guaranteed in datasheet specs; the 60 ps skew limit applies only within the same bank (e.g., CLKA vs CLKB0). Inter-bank skew depends on PCB layout, supply routing, and termination matching. For tight inter-bank alignment, use identical trace lengths and shared VDDO planes with local 0.1 µF bypassing.

What is the function of the PLL_ByPass# pin?

When PLL_ByPass# is asserted LOW, the internal PLL is disabled and the selected input (crystal or Ref_IN) passes directly to the output dividers. This provides deterministic latency and eliminates PLL-induced jitter, useful for synchronous clock forwarding or test modes where phase-locked behavior is unnecessary.