Diodes Incorporated PI6LC48P03LE

Overview

PI6LC48P03LE from Pericom is a 3-output LVPECL clock synthesizer optimized for Ethernet reference clock generation, using a 31.25 MHz or 26.041666 MHz crystal to produce 125/156.25/312.5/625 MHz outputs via 4 frequency-select pins; features ultra-low 0.3 ps RMS phase jitter (12 kHz–20 MHz) at 156.25 MHz and supports dual supply modes (3.3 V or 2.5 V) in a 24-TSSOP package for networking systems.

For engineers reviewing the PI6LC48P03LE datasheet, PI6LC48P03LE pinout, PI6LC48P03LE application, or PI6LC48P03LE equivalent, this device delivers deterministic Ethernet timing with bank-selectable LVPECL outputs, independent output enables, and PLL bypass capability-critical for switch/router PHY clocking, multi-rate SERDES synchronization, and low-jitter system-level clock distribution.

Technical Context

The PI6LC48P03LE implements a proprietary low-phase-noise PLL architecture with separate analog (VDDA), core (VDD), and bank-specific output (VDDOA/VDDOB) power domains to isolate switching noise. Its dual-input interface accepts either a parallel-resonant crystal (26.041666 MHz or 31.25 MHz) or single-ended LVCMOS/LVTTL reference clock via IN_SEL# control.

Frequency synthesis is configured via three 2-bit binary inputs-NA_SEL[1:0] and NB_SEL[1:0] for Bank A/B output dividers, and FBN to select crystal mode-enabling four discrete output frequencies per crystal. Output skew is specified at ≤30 ps within a bank and ≤150 ps across banks under matched load conditions.

Key Specifications

Pinout & Package

Package: 24-pin TSSOP (173 mil wide), lead-free, JEDEC MO-153F/AD compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with IDT8T49N242 and Si5338A-B-GM, the PI6LC48P03LE offers optimal balance of Ethernet-specific frequency set, zero-config hardware programming, and ultra-low jitter-making it ideal for cost-sensitive, high-volume networking hardware where simplicity and jitter performance are prioritized over programmability.

Availability

PI6LC48P03LE is available at Aetrix Electronics and suitable for 10GBASE-T Ethernet PHY clocking, multi-rate switch fabric timing, and industrial Ethernet controller applications requiring stable component supply across commercial and industrial temperature grades.

Supply support for PI6LC48P03LE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance clock, interface, and signal-integrity solutions for networking, computing, and communications markets.

The PI6LC48P03LE belongs to Pericom's HiFlex family-designed specifically for low-jitter, multi-output Ethernet clock generation with hardware-configurable frequency selection and robust power-domain isolation.

FAQ

What crystal specifications are required for stable operation?

The PI6LC48P03LE requires a fundamental-mode parallel-resonant crystal with 18 pF load capacitance, ±20 ppm tolerance, ESR ≤50 Ω, and drive level ≤1 mW. Recommended parts include FY3120001 (31.25 MHz) and FL2600155 (26.041666 MHz). Crystal selection directly impacts RMS phase jitter; deviations beyond spec degrade jitter performance by up to 0.1 ps.

Can the device operate with only one supply voltage?

No. The PI6LC48P03LE requires three independent supply connections: VDD (core logic), VDDA (analog PLL), and VDDOA/VDDOB (LVPECL output banks). Each must be decoupled with 0.1 µF ceramic capacitors; VDDA additionally requires a 10 Ω resistor + 10 µF capacitor network to suppress analog supply noise and maintain sub-0.3 ps jitter.

How is output frequency selected without I²C or configuration registers?

Frequency selection is purely hardware-based using three 2-bit binary inputs: NA_SEL[1:0] and NB_SEL[1:0] for Bank A/B dividers, and FBN to choose crystal mode (0 = 31.25 MHz, 1 = 26.041666 MHz). No firmware or serial interface is needed-frequency is determined at power-on by external pin strapping, enabling immediate clock output after power stabilization.

What happens to outputs during master reset assertion?

When M_reset is driven HIGH, CLKA, CLKA#, CLKB0, CLKB0#, CLKB1, and CLKB1# enter defined logic states: each CLKx pin goes LOW and its complement CLKx# goes HIGH. This provides deterministic, glitch-free output disable-critical for hot-swap and power-sequencing safety in modular networking hardware.