Diodes Incorporated PI6LC48P03LEX

Overview

PI6LC48P03LEX from Pericom is a 3-output LVPECL clock synthesizer optimized for Ethernet reference clock generation, supporting 125 MHz, 156.25 MHz, 312.5 MHz, and 625 MHz outputs via crystal (31.25 MHz or 26.041666 MHz) or single-ended LVCMOS/LVTTL reference input, with ultra-low 0.3 ps RMS phase jitter (12 kHz–20 MHz) at 156.25 MHz, operating on 3.3 V or 2.5 V supplies in commercial temperature range.

For engineers reviewing the PI6LC48P03LEX datasheet, PI6LC48P03LEX pinout, PI6LC48P03LEX application, or PI6LC48P03LEX equivalent, key selection criteria include differential LVPECL output skew (≤120 ps between same-frequency outputs), bank-selectable output dividers (NA_SEL[1:0]/NB_SEL[1:0]), PLL bypass capability, and dual-supply domain isolation (VDDA/VDDO_A/VDDO_B) for jitter-sensitive networking timing systems.

Technical Context

The PI6LC48P03LEX implements a proprietary low-phase-noise PLL architecture with selectable crystal oscillator or LVCMOS/LVTTL reference input, enabling precise frequency synthesis across four standard Ethernet rates. Its dual-output banks (A and B) support independent divider configurations via NA_SEL[1:0] and NB_SEL[1:0], while FBN selects crystal mode (fundamental vs. overtone).

It features three fully independent LVPECL output pairs (CLKA/CLKA#, CLKB0/CLKB0#, CLKB1/CLKB1#), each with dedicated output enable (OEA/OEB) and bank-specific power domains (VDDO_A/VDDO_B), plus analog supply (VDDA) and core supply (VDD) separation to minimize supply-induced jitter coupling into the PLL and outputs.

Key Specifications

Pinout & Package

PI6LC48P03LEX is housed in a 24-pin TSSOP (L) package with 0.65 mm pitch, 173 mil body width, and exposed pad not present. Power supply isolation is implemented via separate VDD (core), VDDA (analog), and VDDO_A/VDDO_B (output bank) pins to suppress supply noise coupling into PLL and outputs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with IDT8T49N242A and Si5338A-B-GM, the PI6LC48P03LEX delivers lower phase jitter (0.3 ps vs. ≥0.5 ps), simpler crystal-based configuration, and lower BOM cost-making it the preferred choice for cost-sensitive, high-volume 10GbE switch and NIC designs where fixed-frequency stability is prioritized over programmability.

Availability

PI6LC48P03LEX is available at Aetrix Electronics and suitable for 10 Gigabit Ethernet switches, optical transport network line cards, network attached storage controllers, and PCIe-to-Ethernet bridge systems requiring stable component supply, consistent lead times, and long-term lifecycle support.

Supply support for PI6LC48P03LEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, signal integrity, and interface solutions for networking, computing, and communications infrastructure.

The PI6LC48P03LEX belongs to Pericom's HiFlex family of clock synthesizers, engineered specifically for ultra-low-jitter Ethernet reference clock generation in carrier-grade and enterprise networking equipment.

FAQ

What crystal specifications are required for PI6LC48P03LEX?

The PI6LC48P03LEX requires either a 31.25 MHz fundamental-mode crystal (FBN = 0) or a 26.041666 MHz overtone-mode crystal (FBN = 1), both with 18 pF load capacitance, ≤50 Ω ESR, and ±20 ppm tolerance. Recommended parts include FY3120001 (31.25 MHz) and FL2600155 (26.041666 MHz), as specified in Pericom's datasheet.

Can PI6LC48P03LEX accept a single-ended clock input instead of a crystal?

Yes. The PI6LC48P03LEX supports LVCMOS/LVTTL single-ended reference input on Ref_IN pin when IN_SEL# is pulled low. The input accepts AC-coupled signals with edge rates down to 10 ns and amplitude reduced to half-swing to minimize rail interference; full-swing signals may degrade jitter performance.

How is power supply filtering implemented for optimal jitter performance?

Optimal jitter requires separate filtering per supply domain: VDD and VDDO pins use 0.1 µF ceramic capacitors; VDDA requires a 10 Ω resistor in series with a 10 µF tantalum capacitor to form an RC low-pass filter that attenuates high-frequency noise coupling into the PLL analog section.

What is the function of PLL_ByPass# and when should it be used?

PLL_ByPass# is an active-low input that disables the internal PLL and passes the selected input clock (crystal or Ref_IN) directly to the output dividers. It is used during system debug, startup validation, or failure recovery to verify clock path functionality independent of PLL lock status.