Diodes Incorporated PI6LC48P03LIE

Overview

PI6LC48P03LIE from Pericom is a 3-output LVPECL clock synthesizer optimized for Ethernet reference clock generation, using a 31.25 MHz or 26.041666 MHz crystal to produce 125/156.25/312.5/625 MHz outputs via 4 frequency-select pins; features ultra-low 0.3 ps (typ) RMS phase jitter (12 kHz–20 MHz) at 156.25 MHz and supports dual 3.3 V / 2.5 V supply modes for networking PHY and MAC timing in industrial-grade systems.

For engineers reviewing the PI6LC48P03LIE datasheet, PI6LC48P03LIE pinout, PI6LC48P03LIE application, or PI6LC48P03LIE equivalent, key selection criteria include LVPECL output skew (≤120 ps between same-frequency outputs), bank-selectable divider control (NA_SEL[1:0]/NB_SEL[1:1]), PLL bypass capability, and industrial −40°C to +85°C operation with separate analog (VDDA), core (VDD), and output (VDDO_A/VDDO_B) power domains.

Technical Context

The PI6LC48P03LIE implements a proprietary low-phase-noise PLL architecture with selectable crystal oscillator or LVCMOS/LVTTL reference input (via IN_SEL#), enabling precise frequency synthesis across four output bands (112–700 MHz). Its dual-bank LVPECL output structure (Bank A: CLKA/CLKA#; Bank B: CLKB0/CLKB0#, CLKB1/CLKB1#) allows independent frequency and enable control per bank using NA_SEL[1:0], NB_SEL[1:1], OEA, and OEB.

Phase jitter performance is maintained through dedicated power domains-VDDA supplies the analog PLL section with RC filtering (10 Ω + 10 μF), while VDDO_A/VDDO_B isolate output drivers-and differential LVPECL termination (150 Ω to GND + 100 Ω across pair) ensures signal integrity at up to 625 MHz with ≤52% duty cycle deviation.

Key Specifications

Pinout & Package

PI6LC48P03LIE is housed in a 24-pin TSSOP (L) package, 173 mil wide, compliant with JEDEC MO-153F/AD mechanical standards and RoHS/Pb-free requirements.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with IDT8T49N242A and Si5338A-B-GM, the PI6LC48P03LIE offers fixed-frequency simplicity, zero-configuration pin-strapped operation, and lower system-level validation effort - ideal for high-volume, cost-sensitive Ethernet PHY timing where flexibility is secondary to reliability and jitter margin.

Availability

PI6LC48P03LIE is available at Aetrix Electronics and suitable for Ethernet switch PHY timing, 10GBase-R line card clocking, and industrial gateway timing requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PI6LC48P03LIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (now part of Diodes Incorporated) specialized in high-performance timing, interface, and signal-integrity solutions for networking, computing, and communications markets.

The PI6LC48P03LIE belongs to Pericom's HiFlex family - engineered specifically for low-jitter Ethernet reference clock generation with pin-strapped frequency selection and industrial-grade robustness.

FAQ

What crystal specifications are required for optimal PI6LC48P03LIE performance?

The PI6LC48P03LIE is characterized for 18 pF parallel-resonant crystals at 31.25 MHz (e.g., FY3120001) or 26.041666 MHz (e.g., FL2600155), with ESR ≤50 Ω, shunt capacitance ≈7 pF, and drive level ≤1 mW. Recommended load capacitors are C1 = 33 pF and C2 = 27 pF to minimize ppm error. Deviations beyond these specs may increase phase jitter or cause start-up failure.

How does the PI6LC48P03LIE handle power supply noise sensitivity?

The PI6LC48P03LIE mitigates power supply noise via three isolated supply domains: VDD (core logic), VDDA (analog PLL with mandatory 10 Ω + 10 µF RC filter), and VDDO_A/VDDO_B (LVPECL outputs, each requiring 0.1 µF local bypass). This separation prevents digital switching noise from modulating the VCO, maintaining sub-0.3 ps RMS jitter even under noisy rail conditions.

Can unused LVPECL outputs be left unconnected without affecting performance?

Yes - all unused LVPECL outputs (e.g., CLKB0/CLKB0# when only CLKA and CLKB1 are needed) may be left floating per datasheet recommendations. No termination or biasing is required, as the internal driver circuitry disables cleanly when corresponding OEA/OEB is deasserted, eliminating stub reflections or DC loading that could degrade active outputs' jitter or skew.

What is the functional impact of asserting PLL_ByPass# on timing behavior?

Asserting PLL_ByPass# (driving it LOW) disables the internal PLL and routes the selected reference input (crystal or Ref_IN) directly to all enabled outputs. This yields deterministic, zero-delay pass-through timing with no PLL lock time or phase alignment - useful for system debug, fail-safe clocking, or applications requiring immediate clock availability before PLL stabilization.