Diodes Incorporated PI6LC48P03LIEX

Overview

PI6LC48P03LIEX from Pericom Semiconductor is a 3-output LVPECL clock synthesizer optimized for Ethernet reference clock generation, supporting 125 MHz, 156.25 MHz, 312.5 MHz, and 625 MHz outputs via pin-selectable dividers, operating from either a 31.25 MHz or 26.041666 MHz crystal, with ultra-low 0.3 ps (typ) RMS phase jitter (12 kHz–20 MHz) at 156.25 MHz, and full 3.3 V / 2.5 V supply compatibility in industrial-temperature TSSOP-24 packaging.

For engineers reviewing the PI6LC48P03LIEX datasheet, PI6LC48P03LIEX pinout, PI6LC48P03LIEX application, or PI6LC48P03LIEX equivalent, key selection criteria include LVPECL output skew (≤120 ps between same-frequency outputs), bank-selectable divider control (NA_SEL[1:0]/NB_SEL[1:0]), PLL bypass capability, and dual-input mode (crystal or LVCMOS reference).

Technical Context

The PI6LC48P03LIEX implements a proprietary low-phase-noise PLL architecture with separate analog (VDDA), core (VDD), and bank-specific output (VDDOA/VDDOB) power domains to isolate switching noise and preserve jitter performance. It supports two crystal frequencies (31.25 MHz or 26.041666 MHz) and uses four frequency-select pins (FBN, NA_SEL[1:0], NB_SEL[1:0]) to configure eight distinct output combinations across two independent LVPECL banks.

Each of its three differential LVPECL output pairs-CLKA/CLKA#, CLKB0/CLKB0#, CLKB1/CLKB1#-is individually enabled via OEA/OEB and assigned to Bank A or Bank B with dedicated divider select logic. The device operates across -40°C to +85°C and supports both crystal oscillator and single-ended LVCMOS/LVTTL reference input modes via IN_SEL# control.

Key Specifications

Pinout & Package

PI6LC48P03LIEX is housed in a 24-pin TSSOP (L) package with 0.65 mm pitch, 173 mil body width, and exposed pad not present. Power integrity is enforced via dedicated VDD (core), VDDA (analog PLL), and VDDOA/VDDOB (Bank A/B output) supplies, each requiring individual 0.1 µF bypassing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with IDT8T49N242A and Si5338A-D-GM, the PI6LC48P03LIEX delivers lower jitter (0.3 ps vs. ≥0.5 ps), eliminates firmware dependency via pin-strapping, and integrates crystal drive - making it optimal for cost-sensitive, fixed-frequency industrial Ethernet hardware where deterministic startup and minimal BOM are critical.

Availability

PI6LC48P03LIEX is available at Aetrix Electronics and suitable for 1G/10G Ethernet switch PHY timing, multi-bank network processor clocking, and optical transport unit (OTU) line cards requiring stable component supply, industrial-temperature operation, and ultra-low-jitter LVPECL outputs.

Supply support for PI6LC48P03LIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, signal integrity, and interface solutions for networking, computing, and communications infrastructure.

The PI6LC48P03LIEX belongs to Pericom's HiFlex family - engineered specifically for low-jitter, multi-output Ethernet reference clock generation with pin-selectable flexibility and industrial reliability.

FAQ

Can PI6LC48P03LIEX operate with a 25 MHz crystal?

No. The device is characterized and specified only for 31.25 MHz or 26.041666 MHz fundamental-mode parallel-resonant crystals. Using a 25 MHz crystal falls outside the recommended crystal specification (28–35 MHz for FBN = 0; 23.33–29.167 MHz for FBN = 1) and will result in invalid output frequencies and degraded phase jitter performance.

What is the maximum allowable skew between CLKA and CLKB0 outputs?

The maximum measured output skew between CLKA and CLKB0 is 150 ps when operating at different frequencies (e.g., 156.25 MHz vs. 125 MHz), as specified in the AC Electrical Characteristics table. This value assumes matched PCB trace lengths, identical termination, and shared VDDO supply domains.

Is external termination required for LVPECL outputs?

Yes. Each LVPECL output pair requires 150 Ω source termination to GND and a 100 Ω AC-coupling resistor across the differential pair (CLKx/CLKx#), per the test circuit in the datasheet. Omitting this causes signal integrity degradation, increased jitter, and potential receiver setup/hold violations.

Does PI6LC48P03LIEX support spread-spectrum clocking (SSC)?

No. The PI6LC48P03LIEX does not implement spread-spectrum modulation. Its PLL is optimized for ultra-low phase jitter, and no SSC control pins, registers, or functional description appear in the datasheet or block diagram - it is a fixed-frequency, low-noise synthesizer only.