Diodes Incorporated PI6LC48P0401LE

Overview

PI6LC48P0401LE from Pericom is a 4-output LVPECL clock generator optimized for Ethernet reference clock synthesis, featuring selectable 156.25 MHz / 125 MHz / 62.5 MHz outputs via N_SEL[1:0] pins, <0.28 ps typical RMS phase jitter (12 kHz–20 MHz), and dual 3.3 V / 2.5 V supply support. It integrates a fixed-M=25 PLL with crystal or LVCMOS reference input, targeting high-integrity timing in 10/100/1000BASE-T systems.

For engineers reviewing the PI6LC48P0401LE datasheet, PI6LC48P0401LE pinout, PI6LC48P0401LE application, or PI6LC48P0401LE equivalent, key selection criteria include differential LVPECL output skew (<120 ps), frequency select pin logic mapping, analog/core/output supply separation (VDDA/VDD/VDDO), and crystal interface design requirements (25 MHz, 18 pF CL, <50 Ω ESR).

Technical Context

The PI6LC48P0401LE implements a PLL-based architecture with fixed M=25 feedback divider and programmable N-divider (÷4, ÷5, ÷10) controlled by N_SEL[1:0], enabling precise Ethernet-compliant frequencies from a 25 MHz fundamental crystal. Its proprietary low-noise VCO delivers sub-0.3 ps RMS jitter across all supported outputs.

It supports dual reference modes: parallel-resonant crystal (XTAL_IN/XTAL_OUT) or single-ended LVCMOS clock (Ref_IN), selected via IN_SEL; PLL operation is enabled when PLL_Bypass = LOW, bypassed when HIGH. All four LVPECL output pairs (CLK0–CLK3) are fully buffered and independently terminated per JEDEC 65-compliant AC-coupled 50 Ω loads.

Key Specifications

Pinout & Package

PI6LC48P0401LE is housed in a Pb-free, green 24-pin TSSOP (173 mil width) package with exposed thermal pad (not electrically connected). Power supply segregation (VDD, VDDA, VDDO) and dedicated ground pins enable low-noise PLL and clean LVPECL output operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock generator applications.

Compared with IDT8T49N242B and Si5338A-B-GM, the PI6LC48P0401LE offers lower jitter at Ethernet-specific frequencies, simpler crystal-based configuration, and lower BOM cost-making it optimal for cost-sensitive, fixed-frequency 10/100/1000BASE-T applications where design-in time and validation effort must be minimized.

Availability

PI6LC48P0401LE is available at Aetrix Electronics and suitable for 10GBASE-T switch designs, industrial Ethernet controllers, and multi-port optical transceiver modules requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for PI6LC48P0401LE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, signal integrity, and interface solutions for networking, computing, and communications markets.

The PI6LC48P0401LE belongs to Pericom's HiFlex family-designed specifically for low-jitter, multi-output Ethernet clock generation with minimal external components and robust crystal interface performance.

FAQ

What crystal specifications are mandatory for stable operation?

The PI6LC48P0401LE requires a 25 MHz fundamental-mode parallel-resonant crystal with 18 pF load capacitance, ≤50 Ω equivalent series resistance (ESR), and ±20 ppm frequency tolerance. Recommended parts include FL2500047 (3.2×2.5 mm) and FY2500091 (5×3.2 mm); deviation beyond these specs risks startup failure or increased jitter.

Can the device operate with only a single-ended reference clock?

Yes. When IN_SEL = HIGH, the device accepts a single-ended LVCMOS or LVTTL clock on Ref_IN (pin 16), supporting 2.5 V or 3.3 V logic levels. The internal pulldown ensures safe default behavior, and the reference is routed directly to the output dividers when PLL_Bypass = HIGH.

How are the four LVPECL outputs electrically isolated from each other?

Each LVPECL output pair (CLK0–CLK3) has its own dedicated VDDO supply pins (pins 3, 5, 22) and shares no internal driver circuitry. The separate VDDO rails, combined with independent output stage biasing, ensure <120 ps inter-output skew and prevent crosstalk-induced jitter coupling between channels.

What is the recommended power supply decoupling strategy?

Each VDD, VDDA, and VDDO pin requires a 0.1 µF ceramic capacitor placed within 2 mm of the pin. VDDA additionally needs a 10 Ω resistor in series with a 10 µF tantalum capacitor to suppress analog supply noise. All supplies must connect directly to the power plane via individual vias to maintain isolation between digital, analog, and output domains.