Diodes Incorporated PI6LC48P0401LEX

Overview

PI6LC48P0401 from Pericom is a 4-output LVPECL clock synthesizer optimized for Ethernet reference clock generation, using a fixed 25MHz crystal and two frequency-select pins (N_SEL[1:0]) to deliver 156.25MHz, 125MHz, or 62.5MHz outputs. It integrates a low-phase-noise VCO achieving 0.23ps typical RMS jitter (1.875MHz–20MHz) at 156.25MHz and operates across -40°C to +85°C with dual 3.3V/2.5V supply support.

For engineers reviewing the PI6LC48P0401 datasheet, PI6LC48P0401 pinout, PI6LC48P0401 application, or PI6LC48P0401 equivalent, this device serves as a high-stability, multi-output networking clock generator requiring precise phase jitter control, differential LVPECL output termination, and flexible reference input selection between crystal and LVCMOS sources.

Technical Context

The PI6LC48P0401 implements a PLL-based architecture with a fixed M-divider of 25 and programmable N-divider values (4, 5, or 10) selected via N_SEL[1:0], enabling three discrete output frequencies from a 25MHz fundamental crystal. Its analog PLL core uses separate VDDA and VDDO supplies to isolate noise-sensitive VCO and output stages.

It supports dual reference modes: crystal oscillator (XTAL_IN/XTAL_OUT) or single-ended LVCMOS/LVTTL (Ref_IN), selected by IN_SEL; PLL operation is enabled or bypassed via PLL_Bypass, allowing direct pass-through of the reference clock to output dividers without phase alignment.

Key Specifications

Pinout & Package

The PI6LC48P0401 is housed in a Pb-free, green 24-pin TSSOP (Package Code L, 173mil width), with dedicated power domains (VDD, VDDA, VDDO), ground separation, and internal pulldown resistors (51kΩ) on all control inputs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with IDT8T49N242 and Si53320-D-GM, the PI6LC48P0401 delivers lower phase jitter and zero-firmware operation via N_SEL pins, making it optimal for fixed-frequency, high-reliability Ethernet systems where deterministic startup and minimal jitter are critical.

Availability

PI6LC48P0401 is available at Aetrix Electronics and suitable for 10GBASE-T PHY clocking, multi-port switch timing, and industrial Ethernet controller applications requiring stable component supply, long-term lifecycle assurance, and consistent electrical performance across temperature extremes.

Supply support for PI6LC48P0401 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, signal integrity, and interface solutions for networking, computing, and communications infrastructure.

The PI6LC48P0401 belongs to Pericom's HiFlex family-designed specifically for low-jitter, multi-output Ethernet clock generation with hardware-selectable frequencies and robust noise isolation across supply domains.

FAQ

What is the minimum required crystal load capacitance for stable 25MHz operation?

The PI6LC48P0401 is characterized for 18pF parallel-resonant crystals. Recommended parts include FL2500047 (3.2×2.5mm, ±20ppm) and FY2500091 (5×3.2mm, ±30ppm). Using crystals with CL ≠ 18pF may cause frequency deviation exceeding ±50ppm due to pullability limits and ESR sensitivity above 50Ω.

Can Ref_IN accept a 1.8V LVCMOS signal when operating at 2.5V VDD?

No. Ref_IN DC specifications require VIH ≥ 1.7V (for VDD = 2.5V ±5%), but the input structure is designed for 2.5V/3.3V logic levels only. A 1.8V signal falls below the guaranteed VIH threshold and may result in unreliable detection or increased jitter due to marginal switching thresholds.

How does PLL_Bypass affect output phase relationship between CLK0 and CLK1?

In PLL_Bypass mode (PLL_Bypass = HIGH), the reference clock passes directly to the output dividers without phase alignment. This eliminates deterministic phase offset between outputs but introduces path-dependent skew-measured at ≤120ps-versus the tighter phase coherence (<50ps) achievable in locked PLL mode.

Is external termination required for LVPECL outputs, and what is the recommended configuration?

Yes. Each LVPECL output pair requires 150Ω source termination to GND on the driver side and a 100Ω AC-coupling capacitor in series with a 50Ω load to GND on the receiver side. This configuration ensures proper common-mode voltage (≈2.0V @ 3.3V supply) and minimizes reflections, preserving signal integrity and jitter performance.