Diodes Incorporated PI6LC48P0401LIE

Overview

PI6LC48P0401LIE from Pericom is a 4-output LVPECL clock generator optimized for Ethernet reference clock synthesis, implementing a fixed-M (M=25) PLL with selectable N-divider (N_SEL[1:0]) to generate 156.25MHz, 125MHz, or 62.5MHz from a 25MHz crystal; features <0.28ps typical RMS phase jitter (12kHz–20MHz), 3.3V/2.5V dual-supply support, and operates from –40°C to +85°C in industrial-grade TSSOP-24.

For engineers reviewing the PI6LC48P0401LIE datasheet, PI6LC48P0401LIE pinout, PI6LC48P0401LIE application, or PI6LC48P0401LIE equivalent, this device serves as a low-jitter, frequency-selectable networking clock source requiring precise LVPECL termination, separate analog/core/output power domains, and validated crystal interface design.

Technical Context

The PI6LC48P0401LIE integrates a proprietary low-phase-noise VCO with a fixed M=25 feedback divider and programmable N-divider (N=4, 5, or 10) controlled by N_SEL[1:0], enabling three discrete output frequencies without external loop filter components. Its PLL_Bypass and IN_SEL pins allow dynamic switching between crystal- and single-ended CMOS reference sources.

It delivers four matched LVPECL differential output pairs (CLK0–CLK3) with ≤120ps inter-output skew, 48–52% duty cycle, and supports both 3.3V and 2.5V supply modes across independent VDD (core), VDDA (analog), and VDDO (output) rails - critical for noise isolation in high-speed Ethernet PHY timing paths.

Key Specifications

Pinout & Package

Package: 24-pin TSSOP (173-mil wide), Pb-free & Green compliant, industrial temperature grade.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock generator applications.

Compared with IDT8T49N242BGI and Si5338A-D-GM, the PI6LC48P0401LIE offers lower jitter (0.28ps vs. ≥0.4ps), simpler pin-strapped configuration, and lower power (130mA vs. ≥200mA), making it optimal for cost-sensitive, fixed-frequency Ethernet timing where minimal design overhead is critical.

Availability

PI6LC48P0401LIE is available at Aetrix Electronics and suitable for 10GBASE-T switches, SFP+ line cards, and industrial Ethernet routers requiring stable component supply, long-term lifecycle assurance, and industrial-temperature qualification.

Supply support for PI6LC48P0401LIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance clock generation, signal integrity, and interface solutions for networking, computing, and communications infrastructure.

The PI6LC48P0401LIE belongs to Pericom's HiFlex family - engineered specifically for low-jitter, multi-output Ethernet reference clocking with minimal external components and robust industrial reliability.

FAQ

What crystal specifications are required for optimal 156.25MHz output performance?

The PI6LC48P0401LIE is characterized for 25MHz parallel-resonant crystals with 18pF load capacitance, ≤50Ω ESR, and ±20ppm stability. Recommended parts include FL2500047 (3.2×2.5mm, 18pF, ±20ppm) and FY2500091 (5×3.2mm, 18pF, ±30ppm). Deviations increase ppm error and degrade jitter performance.

Can the PI6LC48P0401LIE operate with only a single-ended LVCMOS reference input?

Yes - configure IN_SEL = HIGH to route Ref_IN to the PLL, and drive Ref_IN with a 25MHz LVCMOS signal (VIH ≥1.7V @2.5V, ≥2V @3.3V). The device accepts edge rates as slow as 10ns and supports half-swing amplitude to minimize rail interference, but crystal-based operation yields lowest jitter.

How should unused LVPECL outputs be handled on the PCB?

Unused LVPECL outputs (e.g., CLK2/CLK2# when only two clocks are needed) may be left floating with no termination. No pull-up/down resistors are required. However, ensure proper 0.1µF bypass capacitors remain on all VDDO pins, and maintain strict 150Ω source termination on active outputs to preserve signal integrity and jitter performance.

What is the function of the M_reset pin, and what happens during assertion?

M_reset is an active-HIGH asynchronous master reset. When asserted, it forces all true outputs (CLKx) low and inverted outputs (CLKx#) high, halting clock distribution. It resets internal dividers but does not affect PLL lock state. Release (LOW) restores normal operation after ~100µs, with outputs resuming within one reference cycle - no re-lock delay required.