Diodes Incorporated PI6LC48P0401LIEX

Overview

PI6LC48P0401LIEX from Pericom is a 4-output LVPECL clock generator optimized for Ethernet reference clock synthesis, implementing a fixed-M (M=25) PLL with selectable N-divider values (÷4, ÷5, ÷10) to generate 156.25 MHz, 125 MHz, or 62.5 MHz from a 25 MHz crystal. It features separate analog (VDDA), core (VDD), and output (VDDO) supplies, operates from –40°C to +85°C, and achieves 0.23 ps typical RMS phase jitter (1.875 MHz–20 MHz) at 156.25 MHz.

For engineers reviewing the PI6LC48P0401LIEX datasheet, PI6LC48P0401LIEX pinout, PI6LC48P0401LIEX application, or PI6LC48P0401LIEX equivalent, key selection criteria include differential LVPECL output skew (<120 ps), dual supply mode support (2.5 V/3.3 V), frequency select pin logic (N_SEL[1:0]), PLL bypass capability, and crystal interface compliance with 18 pF parallel-resonant crystals.

Technical Context

The PI6LC48P0401LIEX integrates a proprietary low-phase-noise VCO and a fixed-M=25 PLL with programmable N-divider (÷4/÷5/÷10) controlled by two digital inputs (N_SEL0/N_SEL1). Its architecture supports both crystal oscillator (XTAL_IN/XTAL_OUT) and single-ended CMOS reference (Ref_IN) inputs, selected via IN_SEL.

It delivers four matched LVPECL differential output pairs (CLK0–CLK3) with independent termination requirements (150 Ω to GND + 100 Ω across pair), output duty cycle of 48–52%, and rise/fall times ≤400 ps (20%–80%). PLL_Bypass enables direct routing of the reference source to outputs, bypassing the PLL loop for deterministic latency.

Key Specifications

Pinout & Package

PI6LC48P0401LIEX is housed in a Pb-free, green, 24-pin TSSOP (173 mil wide) package per JEDEC MO-153F/AD, with exposed pad not present. Pin assignments are validated per Rev.D datasheet (11/7/2014).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock generator applications.

Compared with ICS8430I-01LFT and Si5338A-B-GM, the PI6LC48P0401LIEX delivers optimal balance of Ethernet-specific frequency coverage, ultra-low jitter, pin-strapped simplicity, and industrial temperature support - making it the most cost-effective and design-efficient choice for fixed-frequency 4-output networking clocking.

Availability

PI6LC48P0401LIEX is available at Aetrix Electronics and suitable for Ethernet switch PHY interface, 10GBASE-T transceiver timing, and industrial network controller applications requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PI6LC48P0401LIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance clock generation, signal integrity, and interface solutions for communications and computing markets.

The PI6LC48P0401LIEX belongs to Pericom's HiFlex family - engineered specifically for low-jitter, multi-output Ethernet reference clocking in switches, routers, and infrastructure equipment where deterministic timing and thermal robustness are critical.

FAQ

What crystal specifications are mandatory for stable 156.25 MHz operation?

The PI6LC48P0401LIEX requires a 25 MHz, parallel-resonant, fundamental-mode crystal with 18 pF load capacitance, ≤50 Ω ESR, and ±20 ppm stability. Pericom validates performance with FL2500047 (3.2×2.5 mm) and FY2500091 (5×3.2 mm) crystals. Deviations in CL or ESR may cause startup failure or increased jitter.

Can the device operate with only a single-ended reference clock and no crystal?

Yes. When IN_SEL is driven HIGH, the device accepts a single-ended LVCMOS/LVTTL clock on Ref_IN (2.5 V or 3.3 V compatible), disabling the XTAL_IN/XTAL_OUT pins. The PLL remains active, and N_SEL[1:0] continues to control output frequency. No external AC-coupling is required for DC-coupled CMOS sources.

How is power supply noise suppressed to maintain sub-0.3 ps jitter?

Jitter integrity relies on strict power domain isolation: VDD (core), VDDA (analog PLL), and VDDO (LVPECL drivers) must be decoupled separately using 0.1 µF ceramic capacitors per pin, plus a 10 µF + 10 Ω RC filter on VDDA. PCB layout must route each supply to its own plane via dedicated vias - mixing domains increases jitter by >0.1 ps.

Is PLL_Bypass mode compatible with all output frequencies?

Yes. PLL_Bypass asserts regardless of N_SEL[1:0] state, routing the selected reference (crystal or Ref_IN) directly to the output dividers. Output frequencies remain unchanged (e.g., 156.25 MHz if N_SEL=00), but phase noise reverts to the reference source's performance - critical for calibration or fail-safe operation where PLL-induced drift must be eliminated.