Diodes Incorporated PI6LC48P0405LIE

Overview

PI6LC48P0405LIE from Pericom Semiconductor is a 4-output LVPECL clock synthesizer optimized for 125MHz Ethernet interface timing, featuring fixed M=25 PLL division, <0.32ps typical RMS phase jitter (12kHz–20MHz), dual supply support (3.3V/2.5V), and operation from –40°C to +85°C in a 24-TSSOP package.

For engineers reviewing the PI6LC48P0405LIE datasheet, PI6LC48P0405LIE pinout, PI6LC48P0405LIE application, or PI6LC48P0405LIE equivalent, key selection criteria include LVPECL output skew (<70ps), crystal vs. single-ended reference input flexibility, PLL bypass capability, and separate VDD/VDDA/VDDO power domains for jitter-sensitive networking clocking.

Technical Context

The PI6LC48P0405LIE integrates a proprietary low-phase-noise VCO with a fixed M=25 integer-N PLL, generating four differential LVPECL outputs at precisely 125MHz when driven by a 25MHz fundamental-mode crystal. Its architecture supports either crystal (XTAL_IN/XTAL_OUT) or LVCMOS/LVTTL single-ended reference (Ref_IN) via IN_SEL control.

It implements three independent power domains-VDD (core logic), VDDA (analog PLL), and VDDO (LVPECL outputs)-enabling noise isolation critical for sub-0.32ps jitter performance. PLL_Bypass allows direct routing of the reference clock to output dividers, bypassing the PLL for deterministic latency or jitter-free pass-through operation.

Key Specifications

Pinout & Package

Package: 24-pin TSSOP (L), Pb-free & Green, 173-mil wide, JEDEC MO-153F/AD compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock synthesizer applications.

Compared with IDT5T9304NLGI and Si5338A-D-GM, the PI6LC48P0405LIE delivers superior jitter performance and true hardware-level PLL bypass - making it optimal for fixed-frequency, ultra-low-jitter Ethernet and SyncE systems where simplicity and deterministic timing are prioritized over programmability.

Availability

PI6LC48P0405LIE is available at Aetrix Electronics and suitable for 10GbE line cards, data center switch fabrics, SyncE equipment clock modules, and optical transport network framer timing requiring stable component supply and industrial-grade thermal reliability.

Supply support for PI6LC48P0405LIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, interface, and signal-integrity solutions for networking, computing, and communications infrastructure.

The PI6LC48P0405LIE belongs to Pericom's HiFlex family - designed specifically for low-jitter, multi-output clock generation in carrier-grade Ethernet and synchronous optical networking equipment.

FAQ

What crystal specifications are required for optimal 125MHz output stability?

The PI6LC48P0405LIE is characterized for 25MHz fundamental-mode parallel-resonant crystals with 18pF load capacitance, ≤50Ω ESR, and 7pF shunt capacitance. Pericom recommends FL2500047 (3.2×2.5mm, ±20ppm) or FY2500091 (5×3.2mm, ±30ppm). External load capacitors C1=33pF and C2=27pF are required to achieve specified ppm accuracy and jitter performance.

Can the PI6LC48P0405LIE operate with mixed supply voltages (e.g., 3.3V VDD and 2.5V VDDO)?

No - all supply pins (VDD, VDDA, VDDO) must be biased at the same nominal voltage: either 3.3V ±5% (3.135–3.465V) or 2.5V ±5% (2.375–2.625V). Mixed-voltage operation is not supported and may cause functional failure or increased jitter due to internal biasing conflicts.

How is output skew measured, and what conditions ensure the <70ps specification?

Output skew is defined as the time difference between differential cross-points of any two LVPECL output pairs under identical supply voltage, equal termination (150Ω to GND + 100Ω across CLK/CLK#), and matched PCB trace lengths. The <70ps maximum is guaranteed across –40°C to +85°C with proper power supply decoupling (0.1µF per VDD/VDDA/VDDO pin, plus 10µF + 10Ω on VDDA).

Is the PLL_Bypass function compatible with both crystal and LVCMOS reference inputs?

Yes - PLL_Bypass operates independently of the reference source selected by IN_SEL. When PLL_Bypass = HIGH, the selected reference (either XTAL_IN or Ref_IN) is routed directly to the output dividers, bypassing the PLL entirely. This provides deterministic latency and eliminates PLL-added jitter regardless of input type.