Diodes Incorporated PI6LC48P0405LIEX

Overview

PI6LC48P0405LIEX from Pericom Semiconductor is a 4-output LVPECL clock generator optimized for 125MHz Ethernet interface timing, featuring fixed M=25 PLL division, <0.32ps typical RMS phase jitter (12kHz–20MHz), and dual 3.3V/2.5V supply operation in a 24-TSSOP package.

For engineers reviewing the PI6LC48P0405LIEX datasheet, PI6LC48P0405LIEX pinout, PI6LC48P0405LIEX application, or PI6LC48P0405LIEX equivalent, key selection criteria include LVPECL output skew (<70ps), crystal vs. LVCMOS reference input flexibility, PLL bypass capability, and industrial temperature support (−40°C to +85°C).

Technical Context

The PI6LC48P0405LIEX integrates a proprietary low-phase-noise VCO with fixed M=25 feedback divider and ÷5 post-divider to generate precise 125MHz LVPECL outputs from a 25MHz crystal or single-ended reference. Its architecture supports both crystal oscillator and LVCMOS/LVTTL input modes via IN_SEL control.

It features three independent power domains-VDD (core), VDDA (analog), and VDDO (outputs)-enabling noise isolation between PLL and outputs. PLL_Bypass allows direct routing of Ref_IN to output dividers, bypassing the PLL for deterministic latency or jitter-sensitive applications.

Key Specifications

Pinout & Package

Package: 24-pin TSSOP (L), Pb-free & Green, 173-mil wide, JEDEC MO-153F/AD compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock generator applications.

Compared with IDT8T49N242BGI and Si5338A-B-GM, the PI6LC48P0405LIEX delivers lower jitter at 125MHz with zero configuration overhead, making it optimal for cost-sensitive, high-volume Ethernet PHY clocking where frequency stability and ease of use outweigh programmability needs.

Availability

PI6LC48P0405LIEX is available at Aetrix Electronics and suitable for 10GbE switches, OTN line cards, NAS controllers, and industrial Ethernet gateways requiring stable component supply and guaranteed industrial temperature performance.

Supply support for PI6LC48P0405LIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance clock management, signal integrity, and interface solutions for networking and communications infrastructure.

The PI6LC48P0405LIEX belongs to Pericom's HiFlex family-designed specifically for low-jitter, multi-output clock generation in Ethernet, Fibre Channel, and telecom applications where deterministic timing and noise isolation are critical.

FAQ

What crystal specifications are required for optimal 125MHz output performance?

The PI6LC48P0405LIEX is characterized with 25MHz parallel-resonant crystals having 18pF load capacitance, ≤50Ω ESR, and ≤7pF shunt capacitance. Pericom recommends FL2500047 (3.2×2.5mm, ±20ppm) or FY2500091 (5×3.2mm, ±30ppm). Crystal layout must include C1=33pF and C2=27pF per datasheet Figure 7 to minimize ppm error and ensure stable startup.

Can the device operate with only a single-ended LVCMOS reference clock and no crystal?

Yes. When IN_SEL is driven HIGH, the device uses Ref_IN as the PLL reference source, disabling the crystal interface. Ref_IN accepts LVCMOS/LVTTL signals at 25MHz with VIH ≥2.0V (3.3V supply) or ≥1.7V (2.5V supply). The input is internally pulldown-biased (51kΩ), so floating is safe but a 1kΩ pull-down is recommended for noise immunity.

How does PLL_Bypass mode affect jitter and system timing behavior?

In PLL_Bypass mode (PLL_Bypass = HIGH), the reference clock is routed directly to the output dividers, eliminating VCO and PLL loop contributions. This reduces RMS phase jitter to the level of the input reference (e.g., ~0.1ps if using a low-noise OCXO) and removes PLL lock time and phase transients-ideal for deterministic clock forwarding in test equipment or retimer applications.

What PCB layout practices are essential to achieve the specified 0.32ps jitter performance?

To achieve datasheet jitter specs, isolate VDD, VDDA, and VDDO with dedicated vias to power planes; place 0.1µF ceramic bypass capacitors within 2mm of each supply pin; add a 10Ω resistor + 10µF capacitor to VDDA per Figure 6; route LVPECL traces differentially with controlled 100Ω impedance; avoid crossing split planes under sensitive analog sections (VDDA, XTAL_IN); and ground unused pins (e.g., NC pins 8,10,12) to reduce parasitic coupling.