Diodes Incorporated PI6LC48P04LIE

Overview

PI6LC48P04LIE from Pericom Semiconductor is a 4-output LVPECL clock synthesizer optimized for Ethernet and Fibre Channel reference clock generation, featuring fixed M=24 PLL architecture, selectable 26.5625 MHz or 26.04166 MHz crystal input, and four differential LVPECL output pairs delivering 212.5/159.375/106.25/53.125/156.25/187.5 MHz frequencies with <0.3 ps typical RMS phase jitter (12 kHz–20 MHz) at 212.5 MHz.

For engineers reviewing the PI6LC48P04LIE datasheet, PI6LC48P04LIE pinout, PI6LC48P04LIE application, or PI6LC48P04LIE equivalent, this device supports precise frequency selection via N_SEL[1:0], dual supply modes (3.3 V / 2.5 V), industrial temperature operation (−40°C to +85°C), and flexible reference source selection (crystal or LVCMOS/LVTTL).

Technical Context

The PI6LC48P04LIE implements a fixed-ratio PLL with M=24 and programmable N-divider values (3, 4, 6, or 12) selected by N_SEL[1:0], enabling six discrete output frequencies across two crystal options. Its proprietary low-phase-noise VCO achieves sub-0.3 ps RMS jitter at 212.5 MHz under 26.5625 MHz crystal excitation.

It supports dual reference paths: parallel-resonant crystal (XTAL_IN/XTAL_OUT) or single-ended LVCMOS/LVTTL clock (Ref_IN), selected via IN_SEL; PLL bypass mode is enabled via PLL_Bypass pin, routing reference directly to output dividers without VCO involvement.

Key Specifications

Pinout & Package

PI6LC48P04LIE is housed in a 24-pin lead-free TSSOP (L) package with exposed thermal pad not connected internally. Power domains are physically separated: VDD (core), VDDA (analog PLL), and VDDO (LVPECL outputs) require individual 0.1 µF bypassing; VDDA additionally needs 10 Ω + 10 µF RC filter per layout guidelines.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with IDT8T49N242BGI and Si5338A-D-GM, the PI6LC48P04LIE offers lowest-system-cost pin-strapped configuration for fixed-frequency Ethernet/Fibre Channel applications, with best-in-class jitter at 212.5 MHz and minimal external component count.

Availability

PI6LC48P04LIE is available at Aetrix Electronics and suitable for Ethernet switch PHY clocking, Fibre Channel line card timing, optical transport network framer sync, and industrial Ethernet controller timing requiring stable component supply across industrial temperature ranges and long production lifecycles.

Supply support for PI6LC48P04LIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance clock management, signal integrity, and interface solutions for networking, computing, and communications infrastructure.

The PI6LC48P04LIE belongs to Pericom's HiFlex family of clock synthesizers, designed specifically to deliver ultra-low-jitter, multi-output reference clocks for 10G/25G Ethernet, Fibre Channel, and OTN systems where deterministic timing and thermal stability are critical.

FAQ

What crystal specifications are required for optimal jitter performance?

The PI6LC48P04LIE is characterized with 18 pF parallel-resonant fundamental-mode crystals at 26.5625 MHz or 26.04166 MHz. Recommended models include FL2650003 (3.2×2.5 mm, ±25 ppm) and FY2650002 (5×3.2 mm, ±30 ppm). ESR must be ≤50 Ω and shunt capacitance ≈7 pF; load capacitance matching is essential to avoid frequency pull and jitter degradation.

Can the PI6LC48P04LIE operate with only a single-ended reference input?

Yes - the Ref_IN pin accepts LVCMOS/LVTTL single-ended clocks. When IN_SEL is HIGH, the internal PLL uses Ref_IN as its reference source. The input edge rate can be as slow as 10 ns, and amplitude should be reduced to half-swing to minimize rail coupling and preserve jitter performance.

How is output skew managed across the four LVPECL channels?

Maximum output skew between any two LVPECL output pairs is guaranteed at ≤70 ps under matched load conditions (150 Ω source + 100 Ω differential termination). This is achieved through matched internal routing and simultaneous edge generation from the same divider tree, ensuring deterministic inter-channel alignment for multi-lane SerDes applications.

What power supply filtering is mandatory for achieving datasheet jitter specs?

To achieve <0.3 ps RMS jitter, each VDD, VDDA, and VDDO pin requires a dedicated 0.1 µF ceramic bypass capacitor placed within 2 mm of the pin. Additionally, VDDA must include a 10 Ω resistor in series with a 10 µF tantalum capacitor to suppress analog-domain noise - omission degrades phase noise by >2 dBc/Hz at 100 kHz offset.