Diodes Incorporated PI6LC48P04LIEX

Overview

PI6LC48P04LIEX from Pericom Semiconductor is a 4-output LVPECL clock synthesizer optimized for Ethernet and Fibre Channel reference clock generation, featuring fixed M=24 PLL architecture, selectable crystal or LVCMOS input, and output frequencies including 212.5MHz, 159.375MHz, 106.25MHz, 53.125MHz, and 156.25MHz. It delivers <0.3ps typical RMS phase jitter (12kHz–20MHz) at 212.5MHz using a 26.5625MHz crystal and operates across -40°C to +85°C in a lead-free 24-TSSOP package.

For engineers reviewing the PI6LC48P04LIEX datasheet, PI6LC48P04LIEX pinout, PI6LC48P04LIEX application, or PI6LC48P04LIEX equivalent, key selection criteria include LVPECL output skew ≤70ps, dual supply mode (3.3V/2.5V), frequency select via N_SEL[1:0], PLL bypass capability, and crystal interface compatibility with 18pF parallel-resonant types.

Technical Context

The PI6LC48P04LIEX implements a fixed-ratio PLL with M=24 and programmable N-divider (N=3,4,6,12) controlled by N_SEL[1:0], enabling five discrete output frequencies from two crystal inputs (26.5625MHz or 26.04166MHz). Its proprietary low-phase-noise VCO achieves 0.3ps typical RMS jitter at 212.5MHz.

It supports dual-reference routing: crystal (XTAL_IN/XTAL_OUT) or single-ended LVCMOS clock (Ref_IN), selected by IN_SEL; PLL operation is enabled when PLL_Bypass = LOW, while HIGH routes reference directly to dividers. All four LVPECL outputs are fully differential, terminated internally per JEDEC 65-compliant 150Ω-to-GND + 100Ω across pair.

Key Specifications

Pinout & Package

Package: 24-pin TSSOP (L), Pb-free & Green, 173mil wide, JEDEC MO-153F/AD compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with IDT8T49N242BGI and Si5338A-D-GM, the PI6LC48P04LIEX offers lowest jitter (0.3ps), zero-config hardware frequency selection, and smallest BOM-ideal for cost-sensitive, high-volume Ethernet/Fibre Channel designs where fixed frequencies suffice.

Availability

PI6LC48P04LIEX is available at Aetrix Electronics and suitable for Ethernet switch fabric, Fibre Channel storage controllers, and optical transport network line cards requiring stable component supply, long-term lifecycle assurance, and industrial-temperature performance.

Supply support for PI6LC48P04LIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, signal integrity, and interface solutions for networking, computing, and communications markets.

The PI6LC48P04LIEX belongs to Pericom's HiFlex family-designed specifically for low-jitter, multi-output clock generation in 10G+ Ethernet and Fibre Channel infrastructure equipment.

FAQ

What crystal specifications are required for optimal PI6LC48P04LIEX performance?

The device is characterized for 18pF parallel-resonant crystals at 26.5625MHz or 26.04166MHz. Recommended parts include FL2650003 (3.2×2.5mm, ±25ppm) and FY2650002 (5×3.2mm, ±30ppm). ESR must be ≤50Ω; shunt capacitance should be 7pF. Deviations increase ppm error and degrade jitter.

Can PI6LC48P04LIEX operate with only a single-ended reference clock?

Yes. When IN_SEL = HIGH, the device accepts a single-ended LVCMOS/LVTTL clock on Ref_IN. The input supports edge rates down to 10ns and benefits from amplitude reduction to half-swing to prevent rail coupling. XTAL_IN/XTAL_OUT are left floating or grounded via 1kΩ resistors in this mode.

How does PLL_Bypass affect timing behavior?

When PLL_Bypass = HIGH, the internal PLL is disabled and the selected reference (crystal or Ref_IN) passes directly to the output dividers. This yields deterministic latency and eliminates PLL lock time, useful for test modes or failover. When LOW, the PLL is active, enabling frequency synthesis and jitter cleanup.

What is the recommended power supply decoupling for PI6LC48P04LIEX?

Each VDD, VDDA, and VDDO pin requires a dedicated 0.1µF ceramic capacitor to ground. Additionally, VDDA needs a 10Ω resistor in series with a 10µF tantalum capacitor to suppress analog supply noise. Power planes must connect via individual vias to minimize shared impedance and preserve jitter performance.