Diodes Incorporated PI6LC48P25104LE

Overview

PI6LC48P25104LE from Pericom is a single-output LVPECL clock synthesizer optimized for Ethernet reference clocks, using a 25MHz crystal to generate 156.25MHz or 187.5MHz outputs with ultra-low phase jitter (0.3ps RMS @156.25MHz), full 3.3V/2.5V supply support, and operation across -40°C to +85°C industrial temperature range.

For engineers reviewing the PI6LC48P25104LE datasheet, PI6LC48P25104LE pinout, PI6LC48P25104LE application, or PI6LC48P25104LE equivalent, key selection criteria include LVPECL output compliance, Freq_SEL-controlled multiplication (×6.25/×7.5), RMS phase jitter performance, crystal interface requirements, and 8-TSSOP lead-free packaging compatibility with SATA/SAS and 10GbE timing systems.

Technical Context

This device implements a proprietary low-phase-noise PLL architecture with separate analog (VDDA) and core (VDD) power domains to isolate switching noise from the VCO and output stage. It accepts fundamental-mode parallel-resonant crystals (23.2–30MHz at Freq_SEL=0; 19.33–25MHz at Freq_SEL=1) and supports LVCMOS single-ended input via AC coupling on XTAL_IN.

The output stage delivers differential LVPECL signals (CLK/CLK#) with 48–52% duty cycle, 400ps rise/fall time (20–80%), and specified termination: 150Ω source-to-GND plus 100Ω across CLK/CLK#. Frequency selection is controlled by a single digital input (Freq_SEL) that selects ×6.25 or ×7.5 multiplication ratios.

Key Specifications

Pinout & Package

Package: 8-pin TSSOP (173mil width), lead-free and RoHS-compliant per Pericom PD-1308 Rev. F.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with IDT8T49N242BGI and Si5338A-D-GM, the PI6LC48P25104LE offers minimal BOM count and layout simplicity for fixed-frequency 10GbE/SATA applications, trading programmability for lower cost, smaller 8-TSSOP footprint, and guaranteed jitter performance without configuration overhead.

Availability

PI6LC48P25104LE is available at Aetrix Electronics and suitable for 10GbE PHY modules, SATA III storage controllers, and industrial Ethernet switch fabric requiring stable component supply, industrial temperature qualification, and lead-free compliance.

Supply support for PI6LC48P25104LE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, interface, and signal-integrity solutions for networking, computing, and communications infrastructure.

The PI6LC48P25104LE belongs to Pericom's HiFlex family of clock synthesizers, designed specifically for low-jitter Ethernet and storage reference clock generation in space-constrained, thermally demanding environments.

FAQ

What crystal specifications are required for stable operation?

The PI6LC48P25104LE requires a fundamental-mode parallel-resonant crystal with 18pF load capacitance, ESR ≤50Ω, shunt capacitance ≤7pF, and drive level ≤1mW. Pericom recommends FL2500047 (25MHz, ±20ppm, 3.2×2.5mm) or FY2500091 (25MHz, ±30ppm, 5×3.2mm). Crystal frequency must fall within 23.2–30MHz (Freq_SEL=0) or 19.33–25MHz (Freq_SEL=1) ranges.

How is LVPECL output termination implemented?

LVPECL termination requires two elements: a 150Ω resistor from each CLK/CLK# output to ground (source termination), and a 100Ω resistor across CLK and CLK# (differential termination). This configuration establishes proper DC bias and ensures signal integrity. AC coupling capacitors (0.01μF) are mandatory before 50Ω scope or receiver inputs to block DC offset.

Can the device operate with a single-ended LVCMOS clock instead of a crystal?

Yes - XTAL_IN accepts AC-coupled LVCMOS clock signals with edge rates up to 10ns. XTAL_OUT should be left floating in this mode. Amplitude should be reduced to half-swing to avoid power rail interference and noise coupling. The device does not require crystal oscillation when driven externally, but performance is guaranteed only with quartz crystals per datasheet validation.

What is the purpose of separate VDD and VDDA pins?

VDD powers the digital PFD and logic sections, while VDDA supplies the analog VCO and charge pump. Separating these rails prevents digital switching noise from modulating the VCO, which directly impacts phase jitter. VDDA requires additional filtering: a 10Ω series resistor and 10μF bulk capacitor, plus a local 0.1μF ceramic bypass, to achieve the specified 0.3ps jitter performance.