Diodes Incorporated PI6LC48P25104LEX

Overview

PI6LC48P25104LEX from Pericom is a single-output LVPECL clock synthesizer optimized for Ethernet reference clocks, using a 25MHz crystal to generate 156.25MHz or 187.5MHz outputs with ultra-low phase jitter (0.3ps RMS @156.25MHz). It supports dual supply modes (3.3V/2.5V), operates from –40°C to +85°C, and is packaged in an 8-pin Pb-free TSSOP.

For engineers reviewing the PI6LC48P25104LEX datasheet, PI6LC48P25104LEX pinout, PI6LC48P25104LEX application, or PI6LC48P25104LEX equivalent, key selection criteria include LVPECL output compliance, Freq_SEL-controlled multiplication (×6.25/×7.5), 145–187.5MHz output range, sub-0.35ps RMS jitter, and separate analog/core power domains (VDDA/VDD).

Technical Context

This device implements a proprietary low-phase-noise PLL architecture with integrated VCO and PFD, accepting fundamental-mode crystals (19.33–30MHz) and supporting LVCMOS single-ended input via AC coupling. Frequency selection is controlled by a single digital input (Freq_SEL) that configures integer multiplication factors of 6.25 or 7.5.

The IC features split power domains-VDDA for analog circuitry (including crystal oscillator and PLL) and VDD for digital logic-enabling noise isolation critical for jitter-sensitive applications. Output termination requires 150Ω source-to-GND plus 100Ω differential load across CLK/CLK#.

Key Specifications

Pinout & Package

Package: 8-pin TSSOP (173 mil width), lead-free and RoHS-compliant, with exposed pad not present. Thermal resistance: θ_JA = 124.0°C/W (still air).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with IDT8T49N242BGI and Si5338A-D-GM, the PI6LC48P25104LEX offers lower cost, minimal footprint (8-TSSOP), and zero-config operation-ideal for fixed-frequency Ethernet/SAS systems where simplicity and jitter performance are prioritized over programmability.

Availability

PI6LC48P25104LEX is available at Aetrix Electronics and suitable for Ethernet switches, SAS storage controllers, and industrial network interface modules requiring stable component supply with industrial temperature support and Pb-free compliance.

Supply support for PI6LC48P25104LEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, interface, and signal-integrity solutions for networking and computing infrastructure.

The PI6LC48P25104LEX belongs to the HiFlex family of clock synthesizers, designed specifically to deliver ultra-low-jitter, single-output LVPECL clocks for Ethernet, SATA, and SAS applications without requiring programmability or external memory.

FAQ

What crystal specifications are required for stable 156.25MHz output?

The PI6LC48P25104LEX requires a 25MHz fundamental-mode parallel-resonant crystal with 18pF load capacitance, ±20ppm tolerance, and ≤50Ω ESR. Pericom recommends FL2500047 (3.2×2.5mm) or FY2500091 (5×3.2mm); deviation outside these specs risks frequency error >±50ppm or startup failure.

Can the XTAL_IN pin accept a CMOS clock signal instead of a crystal?

Yes-XTAL_IN accepts AC-coupled LVCMOS signals (e.g., from an FPGA or MCU) with amplitude reduced to half-swing (≈1.25V for 2.5V rail) and edge rate ≥10ns. XTAL_OUT must be left floating in this mode, and crystal-related components (C1/C2) are omitted per datasheet Figure 11.

How does Freq_SEL determine output frequency?

Freq_SEL sets the integer multiplication factor: logic LOW selects ×6.25 (e.g., 25MHz × 6.25 = 156.25MHz); logic HIGH selects ×7.5 (25MHz × 7.5 = 187.5MHz). The input crystal frequency must be chosen to yield target output within 145–187.5MHz range per the Output Frequency Table.

Why are separate VDD and VDDA supplies required?

VDD powers digital logic (PFD, counters), while VDDA powers analog blocks (crystal oscillator, VCO, charge pump). Separating them prevents digital switching noise from modulating the VCO, which would increase phase jitter. Each requires dedicated 0.1μF bypassing; VDDA additionally needs a 10Ω + 10μF RC filter per datasheet Section 5.