Diodes Incorporated PI6LC48P25104LIE

Overview

PI6LC48P25104LIE from Pericom is a single-output LVPECL clock synthesizer optimized for Ethernet reference clock generation, using a 25MHz crystal to produce 156.25MHz or 187.5MHz outputs with ultra-low phase jitter (0.3ps RMS @156.25MHz), full 3.3V/2.5V supply support, and industrial temperature range operation (-40°C to +85°C).

For engineers reviewing the PI6LC48P25104LIE datasheet, PI6LC48P25104LIE pinout, PI6LC48P25104LIE application, or PI6LC48P25104LIE equivalent, this device delivers deterministic low-jitter timing for high-speed serial interfaces where phase noise directly impacts bit error rate and link stability in 10GbE, SATA, and SAS systems.

Technical Context

This synthesizer integrates a proprietary low-phase-noise PLL with a programmable frequency multiplier (×6.25 or ×7.5 via Freq_SEL) and on-chip crystal oscillator circuitry. It accepts fundamental-mode parallel-resonant crystals (19.33–30MHz) and supports both LVPECL differential output termination (150Ω to GND + 100Ω across CLK/CLK#) and LVCMOS single-ended crystal input via AC coupling.

The device separates analog (VDDA) and core (VDD) power domains to isolate PLL noise from output drivers, requiring dedicated 0.1μF bypassing per supply and an additional 10Ω + 10μF RC filter on VDDA to meet sub-0.35ps jitter targets under industrial thermal conditions.

Key Specifications

Pinout & Package

Package: 8-pin Pb-free TSSOP (173mil width), JEDEC MO-153F/AA compliant, thermal resistance QJA = 124°C/W (still air).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL clock synthesizer applications.

Compared with IDT8T49N242A and Si5338A-B-GM, the PI6LC48P25104LIE offers lowest phase jitter and zero-configuration operation at the cost of fixed output frequencies and external crystal dependency-ideal for cost-sensitive, high-volume Ethernet timing applications.

Availability

PI6LC48P25104LIE is available at Aetrix Electronics and suitable for 10GbE PHY clocking, SATA/SAS host controller timing, and industrial network switch timing requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PI6LC48P25104LIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, signal integrity, and interface solutions for networking, computing, and communications infrastructure.

The HiFlex family-including PI6LC48P25104LIE-is engineered specifically for low-jitter Ethernet and storage reference clock generation, emphasizing simplicity, reliability, and compliance with IEEE and ANSI jitter standards.

FAQ

What crystal specifications are mandatory for stable operation?

The PI6LC48P25104LIE requires a fundamental-mode parallel-resonant crystal with 18pF load capacitance, ESR ≤50Ω, and frequency tolerance of ±20ppm or better. Pericom recommends FL2500047 (25MHz, 3.2×2.5mm, CL=18pF) or FY2500091 (25MHz, 5×3.2mm, CL=18pF). Deviations risk startup failure or increased phase jitter.

Can the device operate with a 2.5V supply only, or must both 2.5V and 3.3V be present?

The PI6LC48P25104LIE supports either 3.3V or 2.5V operation across both VDD and VDDA pins-no mixed-voltage operation is allowed. Both supplies must be set to the same nominal voltage (e.g., all 2.5V or all 3.3V), as internal regulators are not present and rail mismatch causes functional failure.

How does Freq_SEL pin state affect output frequency selection?

When Freq_SEL is pulled LOW (≤0.8V), the internal PLL multiplies the crystal frequency by 6.25 (e.g., 25MHz → 156.25MHz). When pulled HIGH (≥2.0V), multiplication is ×7.5 (e.g., 25MHz → 187.5MHz). The pin has internal pull-down, so no external resistor is needed for default 156.25MHz operation.

Is LVCMOS clock input supported, and what are the interface requirements?

Yes-XTAL_IN accepts AC-coupled LVCMOS signals (10ns max edge rate). A 0.1μF series capacitor is required; the driver should be half-swing (1.25V for 2.5V rail) to avoid rail interference. XTAL_OUT must be left floating in this mode. Full-swing LVCMOS may cause excessive noise and violate jitter specs.