Diodes Incorporated PI6LC48S0401ZLIEX

Overview

PI6LC48S0401ZLIEX from Diodes Incorporated is a 5-output, LC-VCO-based Ethernet clock generator with integrated PLL, supporting 156.25 MHz, 125 MHz, 100 MHz, 50 MHz, and 25 MHz outputs via selectable dividers. It accepts 25 MHz crystal or differential (25/125/156.25 MHz) reference inputs, delivers LVPECL/LVDS outputs, and operates from 2.5 V or 3.3 V supplies across –40°C to +85°C for 10GbE and multi-rate Ethernet timing.

For engineers reviewing the PI6LC48S0401ZLIEX datasheet, PI6LC48S0401ZLIEX pinout, PI6LC48S0401ZLIEX application, or PI6LC48S0401ZLIEX equivalent, key selection criteria include integrated phase noise (0.25 ps RMS @ 156.25 MHz), I²C + pin-strapping configuration flexibility, dual-supply voltage support (2.5 V / 3.3 V), industrial temperature range, and differential output signaling control per channel.

Technical Context

The device implements an LC-based VCO architecture with programmable feedback dividers and input multiplexing between crystal oscillator (X_IN/X_OUT) and differential reference (IN+/IN−). Its PLL supports bypass mode for direct clock distribution and features tri-level control pins (INFREQ_SEL, FS_Q, MODE0/MODE1) for frequency, output type, and enable configuration without I²C.

It integrates separate power domains-VDD (core), VDDA (analog), and VDDO (outputs)-with –52 dBc typical PSNR on VDD and –65 dBc on VDDA, enabling robust operation in noisy board environments. Output signaling (LVPECL or LVDS) is configurable per output pair via register or pin control, with independent enable/disable per Q0–Q4.

Key Specifications

Pinout & Package

Package: 48-contact, 6 mm × 6 mm, 0.5 mm pitch TQFN (Pb-free & Green, ZL code), with exposed thermal pad connected to GND.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Ethernet clock generator applications.

Compared with Si5332A-D-GM and ICS8430I-01T, the PI6LC48S0401ZLIEX uniquely balances Ethernet-specific frequency agility, dual LVPECL/LVDS output signaling, PLL bypass capability, and industrial temperature support in a single 6×6 mm package-making it optimal for mid-complexity, thermally demanding Ethernet systems.

Availability

PI6LC48S0401ZLIEX is available at Aetrix Electronics and suitable for 10GbE line cards, multi-rate Ethernet switches, industrial gateways, and OTN framer timing applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for PI6LC48S0401ZLIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors, analog ICs, and timing solutions, headquartered in Plano, Texas, with design centers and manufacturing operations across Asia and the Americas.

The PI6LC48S0401 belongs to Diodes' Pericom-branded HiFlex™ Ethernet clock generator product line, engineered specifically to simplify clock tree design in multi-rate Ethernet infrastructure equipment while meeting stringent jitter and thermal reliability requirements.

FAQ

Can PI6LC48S0401ZLIEX operate with a 25 MHz fundamental-mode crystal only, or does it require a specific load capacitance?

Yes, it operates with a 25 MHz fundamental-mode crystal. The datasheet specifies 18 pF load capacitance (C_L) and recommends C1/C2 = 18 pF each for optimal start-up and ppm accuracy. Internal crystal circuit capacitance is 12 pF, and ESR must be ≤50 Ω. Crystals like SaRonix-eCera FL2500047 (25 MHz, ±20 ppm, CL = 18 pF) are validated for use.

What is the functional difference between PLL_BYPASS mode and normal PLL mode?

In PLL_BYPASS mode (PLL_BYPASS = high), the reference input (crystal or differential) is routed directly to all enabled outputs without VCO multiplication or division-preserving input jitter and eliminating PLL-induced noise. In normal mode, the LC-VCO locks to the reference and generates multiplied/divided outputs, enabling 156.25 MHz from 25 MHz. Bypass mode is used for lowest possible jitter or when input frequency matches required output.

How does the device handle power supply noise on VDDO, and what is the impact on output jitter?

VDDO supplies the differential output drivers. The datasheet specifies –50 dBc typical PSNR on VDDO (10 kHz–1.5 MHz), meaning a 50 mV_pp noise signal couples to the output with –50 dB attenuation. This translates to ~0.0056 V_pp residual noise on the output, contributing minimally to jitter-verified by measured 0.25 ps RMS phase jitter at 156.25 MHz under full VDDO noise stress.

Is I²C communication required to configure output frequencies, or can pin-strapping alone suffice?

Pin-strapping alone fully configures output frequencies, signaling type, and enable states using INFREQ_SEL, FS_Q, MODE0, and MODE1-no I²C needed for basic operation. I²C is optional and used only for dynamic reconfiguration (e.g., changing frequency during runtime) or accessing advanced registers like individual output enables (Byte 2) or vendor ID (Byte 0).