Diodes Incorporated PI6LC48S04ZHIEX

Overview

PI6LC48S04ZHIEX from Diodes Incorporated is a 4-output, low-jitter clock synthesizer generating selectable 100/125/156.25/250MHz differential clocks from a 25MHz fundamental-mode crystal; features two LVDS and two low-power HCSL outputs, 0.21ps RMS phase jitter (1–20MHz), -50dB PSNR, and operates across -40°C to 85°C for serial reference clocking in PCIe Gen3/4 and Ethernet PHY timing applications.

For engineers reviewing the PI6LC48S04ZHIEX datasheet, PI6LC48S04ZHIEX pinout, PI6LC48S04ZHIEX application, or PI6LC48S04ZHIEX equivalent, key selection criteria include output format compatibility (LVDS/HCSL), PLL bypass capability, frequency select control timing, VSWING_CTRL programmable amplitude, and TQFN-32 thermal performance under 2.5V/3.3V supply.

Technical Context

The PI6LC48S04 integrates a PLL with 25× multiplication factor and configurable integer output dividers (N = 4, 5, 10) to synthesize four synchronized clocks from a single 25MHz crystal or external REF_CLK. Its dual-bank architecture isolates QA (LVDS) and QB (low-power HCSL) outputs with independent supply rails (VDDOA/VDDOB) and dedicated enable controls (nOEA/nOEB).

Phase noise is optimized via analog power separation (VDDA), on-chip LPF tuning, and crystal interface design supporting 18pF parallel-resonant crystals. The VSWING_CTRL pin provides tri-level swing control (0.63/0.75/0.87V) for HCSL outputs, while asynchronous F_SEL[1:0], REF_SEL, BYPASS, and enable inputs allow dynamic reconfiguration without PLL unlock.

Key Specifications

Pinout & Package

PI6LC48S04ZHIEX is housed in a RoHS-compliant, lead-free 32-pin Thin Quad Flat No-Lead (TQFN) package (code ZH), measuring 5mm × 5mm with 0.5mm pitch and an exposed thermal pad for enhanced thermal management. Pin numbering follows standard counter-clockwise orientation starting from top-left corner (Pin 1).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock synthesizer applications.

Compared with ICS8430I-01LG and Si5332A-D-EVB, PI6LC48S04ZHIEX delivers optimal balance of jitter performance, dual-output format support, and plug-and-play crystal operation - making it the most efficient choice for PCIe Gen3/4 and 10GbE reference clock generation without configuration overhead.

Availability

PI6LC48S04ZHIEX is available at Aetrix Electronics and suitable for PCIe Gen4 server motherboards, 10GbE telecom line cards, SATA III/USB 3.0 storage controllers, and industrial embedded gateways requiring stable component supply with guaranteed long-term availability.

Supply support for PI6LC48S04ZHIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs, with leadership in timing, power management, and signal integrity solutions for communications and computing markets.

The PI6LC48S04 belongs to Diodes' HiFlex Serial Interface Clock family, engineered specifically for low-jitter, multi-format reference clock generation in high-speed serial protocols including PCIe, SATA, USB, and Ethernet.

FAQ

What crystal specifications are required for optimal jitter performance?

The PI6LC48S04ZHIEX is characterized with a 25MHz, fundamental-mode, parallel-resonant crystal having 18pF load capacitance and ≤80Ω ESR. Using this specification ensures 0.21ps RMS phase jitter (1–20MHz). Deviations - especially higher ESR or incorrect load capacitance - increase jitter and may prevent reliable PLL lock. External load capacitors are not needed due to internal matching.

Can the device operate with both 2.5V and 3.3V supplies simultaneously?

Yes - VDD (core), VDDA (analog), VDDOA (LVDS outputs), and VDDOB (HCSL outputs) all support either 2.5V ±5% or 3.3V ±5%, and may be mixed across rails. For example, VDD/VDDA can run at 3.3V while VDDOA/VDDOB operate at 2.5V to match downstream LVDS/HCSL receiver voltage domains - enabling flexible power domain partitioning without level shifters.

How does the VSWING_CTRL pin affect HCSL output compliance?

VSWING_CTRL sets the differential amplitude of QB0±/QB1± outputs to 0.63V (pin = 0), 0.75V (pin = open), or 0.87V (pin = 1). This directly determines eye height and noise margin at the receiver. For example, 0.75V aligns with standard 10GbE PHY thresholds, while 0.63V reduces power in dense layouts. Amplitude is measured across the 100Ω differential termination at the load.

Is PLL bypass mode functional with the crystal input?

Yes - when BYPASS = 1 and REF_SEL = 0, the device routes the 25MHz crystal signal directly through the output dividers (N = 4, 5, 10, or 25) without PLL multiplication. This yields deterministic 100/125/156.25/250MHz outputs but with uncleaned jitter (≈1ps RMS). It is intended for boot-time operation or fail-safe modes where phase alignment is less critical than deterministic timing.