Diodes Incorporated PI6LC48S25AZBBIE

Overview

PI6LC48S25AZBBIE from Pericom Semiconductor is a low-phase-noise LC-VCO-based Ethernet network clock generator optimized for 10GbE systems. It accepts a 25MHz crystal or differential reference (25/125/156.25MHz), generates synchronized outputs at 312.5/156.25/125/100/50/25MHz, supports LVPECL/LVDS signaling per bank, and operates from -40°C to +85°C with 2.5V/3.3V supplies.

For engineers reviewing the PI6LC48S25AZBBIE datasheet, PI6LC48S25AZBBIE pinout, PI6LC48S25AZBBIE application, or PI6LC48S25AZBBIE equivalent, key selection criteria include integrated phase noise (0.3ps RMS @156.25MHz), PLL bypass mode for test, I²C + pin-strapping configuration flexibility, and 4 independent output banks with selectable signaling and frequency division.

Technical Context

The device implements an LC-based VCO architecture with a high-stability PLL loop optimized for jitter-sensitive 10GbE timing. Input multiplexing selects between crystal (X_IN/X_OUT) and differential inputs (IN+/IN−), while INFREQ_SEL configures reference frequency interpretation (25/125/156.25MHz).

Four output banks (A–D) are independently configurable via tri-level pins or I²C: Bank A supports 312.5/156.25/125/100MHz; Banks B/C support 156.25/125/100/50MHz; Bank D provides dual CMOS/differential outputs with FS_D0/FS_D1 control. PLL_BYPASS routes input directly to Banks A–C for deterministic latency testing.

Key Specifications

Pinout & Package

Package: 56-lead 8×8mm Pb-free Green TQFN (ZBB) with exposed thermal pad (E-pad) connected to GND.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Ethernet clock generator applications.

Compared with Si5332-D-GM and ICS8430I-01T, the PI6LC48S25AZBBIE uniquely integrates a crystal oscillator buffer, pin-strapped multi-rate flexibility, and PLL bypass-making it optimal for embedded 10GbE designs requiring both simplicity and test readiness.

Availability

PI6LC48S25AZBBIE is available at Aetrix Electronics and suitable for 10GbE switch line cards, multi-rate optical transceivers, and industrial Ethernet controllers requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PI6LC48S25AZBBIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, interface, and signal-integrity solutions for networking and computing infrastructure.

The PI6LC48S25A belongs to Pericom's HiFlex™ Ethernet clock generator family, designed specifically to simplify clock tree design in multi-rate, multi-protocol 10GbE and beyond-10G systems with low jitter and flexible configuration.

FAQ

What is the function of the X_OUT pin?

X_OUT is a buffered, low-noise output of the internal crystal oscillator circuit. It provides a clean 25MHz reference signal usable by other ICs on the board-eliminating the need for an external crystal buffer and reducing component count and jitter accumulation in multi-clock-domain systems.

Can the PI6LC48S25AZBBIE generate 25MHz and 156.25MHz simultaneously?

Yes. Bank A can be configured for 156.25MHz (FS_A=0), Bank B for 125MHz (FS_B=1), Bank C for 50MHz (FS_C=1), and Bank D for 25MHz (FS_D0=1, FS_D1=1). All four banks operate concurrently with independent signaling and load drive capability.

How does PLL_BYPASS affect output timing behavior?

When PLL_BYPASS = 1, the input reference (crystal or differential) is routed directly to Banks A, B, and C without PLL multiplication. This eliminates PLL-induced jitter and lock time, enabling deterministic, zero-delay clock distribution for board-level functional testing and debug.

Is I²C required to configure output frequencies?

No. All frequency selections (FS_A–FS_D1) and output type controls (QA_Mode–QD_Mode) are implemented via tri-level pins, allowing full configuration at power-up without I²C. I²C is optional for dynamic reprogramming during operation or fine-grained register access.