Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Diodes Incorporated PI6LC48S25AZBBIEX

Name: PI6LC48S25AZBBIEX
Brand: Diodes Incorporated
SKU: PI6LC48S25AZBBIEX
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: PI6LC48S25AZBBIEX

Manufacturer:: Diodes Incorporated

Category:: Application Specific Clock/Timing

Package:: 56-VFQFN Exposed Pad

Datasheet:: PI6LC48S25AZBBIEX.pdf

Description:: HIFLEX ETHERNET NETWORK CLOCK GE

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,066

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

PI6LC48S25AZBBIEX from Pericom Semiconductor is a low-phase-noise LC-VCO-based Ethernet network clock generator designed for 10GbE systems. It accepts 25 MHz crystal or 25/125/156.25 MHz differential inputs, delivers up to six output frequencies (312.5/156.25/125/100/50/25 MHz), supports LVPECL/LVDS signaling across four banks, and operates from -40°C to +85°C in a 56-pin 8×8 mm TQFN package.

For engineers reviewing the PI6LC48S25AZBBIEX datasheet, PI6LC48S25AZBBIEX pinout, PI6LC48S25AZBBIEX application, or PI6LC48S25AZBBIEX equivalent, key selection criteria include integrated phase noise (0.3 ps RMS @ 156.25 MHz), PLL bypass mode for test, I²C + pin-strapping configuration flexibility, and power supply noise rejection (-52 dBc @ VDD).

Technical Context

The device implements an LC-based VCO architecture with a programmable PLL loop optimized for jitter-sensitive 10GbE timing. Input multiplexing supports either 25 MHz crystal (X_IN/X_OUT) or differential reference (IN+/IN-) via IN_SEL control, while INFREQ_SEL selects between 25/125/156.25 MHz reference sources.

Four independent output banks (A–D) provide frequency- and signaling-configurable outputs: Bank A–C support LVPECL/LVDS with tri-level FS_A/B/C controls; Bank D offers dual-mode LVPECL/LVDS plus CMOS (QD0/QD1) with separate FS_D0/FS_D1 and slew rate control (SLEW_CMOS).

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage	2.5 V or 3.3 V core & analog supplies - enables interoperability with both legacy 2.5 V and modern 3.3 V system rails.
Input Frequency Support	25 MHz crystal, or 25/125/156.25 MHz differential - covers primary Ethernet reference standards including 10GbE, SFI, XAUI, and CPRI.
Output Frequencies	312.5 / 156.25 / 125 / 100 / 50 / 25 MHz - matches IEEE 802.3ae, ITU-T G.709, and SONET OC-48/192 line rates.
Integrated Phase Jitter	0.3 ps RMS (12 kHz–20 MHz, 156.25 MHz output) - meets stringent 10GbE jitter budget requirements for SERDES clocking.
Power Supply Noise Rejection	-52 dBc @ VDD, -65 dBc @ VDDA - suppresses board-level switching noise from adjacent digital circuits without external filtering.
Output Signaling Options	LVPECL or LVDS per bank (A–D), plus CMOS on Bank D - allows direct interface to diverse PHYs, FPGAs, and ASICs without level-shifting.
Configuration Interface	Pin-strapped tri-level logic + I²C (7-bit address DC_h/DE_h) - supports both simple hardware setup and dynamic runtime reconfiguration.

Pinout & Package

Package: 56-lead, 8 mm × 8 mm, 0.5 mm pitch, Pb-free & Green TQFN (ZBB) with exposed thermal pad (E-pad) connected to GND.

Pin/Terminal	Circuit Role	Design Meaning
1–2, 27, 44 (VDD)	Core power supply	Supplies 2.5 V or 3.3 V to internal logic and PLL; requires local 0.1 µF + 10 µF decoupling.
4–5 (IN+, IN-)	Differential reference input	Accepts AC-coupled LVPECL, LVDS, CML, or HCSL; includes internal 100 Ω termination resistor.
7 (X_IN/CLK), 8 (X_OUT)	Crystal oscillator interface	Drives parallel-resonant 25 MHz crystal (CL = 18 pF); supports buffered XO output for low-noise system reference.
9 (PLL_BYPASS)	PLL enable/disable control	When high, routes input clock directly to Banks A/B/C - enables functional test without PLL lock dependency.
15 (SCLK), 16 (SDATA)	I²C serial interface	Supports block read/write; internal 50 kΩ pull-ups allow minimal external components for basic configuration.
47–48 (QA+, QA-), 23–24 (QD0+, QD0-), etc.	Differential clock outputs	Each bank (A–D) has dedicated VDD_Ox supplies and tri-level mode control (QA_Mode, QD_Mode) for LVPECL/LVDS selection.
20 (QD1)	CMOS clock output	Bank D's single-ended CMOS output supports 25/100/125 MHz; slew rate controlled by SLEW_CMOS pin (pin 28).

Key Features

Feature	Design Value
Low-jitter LC-VCO architecture	0.3 ps integrated phase noise at 156.25 MHz enables compliance with 10GbE SERDES jitter masks (IEEE 802.3ae Annex 48A).
Multi-bank output flexibility	Four independent banks with selectable LVPECL/LVDS signaling and per-bank frequency dividers - eliminates need for multiple discrete clock ICs.
Dual configuration modes	Hardware pin-strapping (tri-level logic) + full I²C register access - supports both factory-set and field-upgradable timing configurations.
Robust supply noise immunity	-52 dBc PSNR on VDD and -65 dBc on VDDA - maintains output jitter integrity in noisy mixed-signal PCB environments.
Crystal oscillator buffer output	X_OUT provides low-noise 25 MHz reference for auxiliary circuitry (e.g., management MCU or ADC clocks), reducing BOM count.

Applications

10GbE Line Cards

SFP+ / QSFP+ Modules

Use Scenario: High-density 10GbE switch/router line cards requiring synchronous multi-port clocking with sub-0.5 ps jitter.

IC Role / Device Role / Timing Role: Primary clock generator providing 156.25 MHz (XAUI), 312.5 MHz (XFI), and 125 MHz (SGMII) to multiple SerDes lanes and MAC controllers.

Use Value: Single-chip solution replaces discrete PLL + fanout buffers, reducing layout area by >40% and eliminating inter-chip skew.

Use Scenario: Pluggable optical transceivers needing compact, low-power, and thermally robust clock synthesis.

IC Role / Device Role / Timing Role: Embedded clock source generating 156.25 MHz differential clocks for host-side SerDes and 25 MHz for module microcontroller.

Use Value: 8×8 mm TQFN package fits within QSFP+ mechanical envelope; industrial temp rating (-40°C to +85°C) ensures reliability in uncontrolled chassis environments.

CPRI Baseband Units

OTN Transport Equipment

Use Scenario: Wireless baseband units implementing CPRI v6+ with 307.2 MHz or 245.76 MHz sampling clocks derived from 156.25 MHz reference.

IC Role / Device Role / Timing Role: Reference clock multiplier generating 312.5 MHz output (2×156.25 MHz) with ultra-low jitter for DAC/ADC sampling clocks.

Use Value: Integrated phase noise performance avoids need for external jitter cleaners, simplifying RF front-end timing architecture.

Use Scenario: OTN (ITU-T G.709) transport gear requiring precise 156.25 MHz, 125 MHz, and 100 MHz clocks for client mapping and FEC processing.

IC Role / Device Role / Timing Role: Multi-frequency clock source feeding OTN framer, mapper, and forward error correction ASICs simultaneously.

Use Value: Independent bank control allows concurrent generation of non-harmonically related frequencies (e.g., 156.25 MHz + 100 MHz) without shared divider constraints.

Equivalent & Alternatives

The following parts are listed as comparable options for similar Ethernet clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
IDT8T49N242A	Uses ring-VCO (not LC-VCO); higher typical phase noise (0.45 ps RMS @ 156.25 MHz); supports JESD204B but lacks crystal oscillator buffer.	Better suited for JESD204B-compliant data converters; less optimal for pure Ethernet PHY clocking where crystal buffering is critical.	Choose when JESD204B timing is required and crystal buffer is unnecessary.
Si5338A-B-GM	Multi-output clock generator with fractional-N synthesizer; wider frequency range (0.16–350 MHz); higher power (120 mA vs. 525 mA max for PI6LC48S25A).	Preferred for heterogeneous systems needing arbitrary frequencies; over-engineered for fixed Ethernet rates where simplicity and jitter matter most.	Choose when flexible frequency synthesis across non-standard rates is mandatory.

Compared with IDT8T49N242A and Si5338A-B-GM, the PI6LC48S25AZBBIEX delivers superior jitter performance specifically tuned for 10GbE, integrates a low-noise crystal buffer, and uses simpler configuration - making it optimal for cost- and jitter-sensitive Ethernet infrastructure.

Availability

PI6LC48S25AZBBIEX is available at Aetrix Electronics and suitable for 10GbE line cards, SFP+/QSFP+ modules, and CPRI baseband units requiring stable component supply, long-term lifecycle assurance, and industrial temperature operation.

Supply support for PI6LC48S25AZBBIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, signal integrity, and interface solutions for networking and communications infrastructure.

The PI6LC48S25A belongs to Pericom's HiFlex™ Ethernet Clock Generator family, engineered specifically to meet the low-jitter, multi-rate, and configurability demands of 10GbE, CPRI, and OTN timing subsystems.

FAQ

What input references does the PI6LC48S25AZBBIEX support?

The device accepts a 25 MHz parallel-resonant crystal (via X_IN/X_OUT pins) or differential AC-coupled signals at 25 MHz, 125 MHz, or 156.25 MHz on IN+/IN-. Input selection is controlled by the IN_SEL pin, and reference frequency is configured via INFREQ_SEL. Crystal load capacitance is specified at 18 pF, and internal oscillator bias supports fundamental-mode crystals only.

How is output signaling selected for each bank?

Each output bank (A–D) uses dedicated tri-level control pins (e.g., QA_Mode, QB_Mode0/QB_Mode1, QC_Mode, QD_Mode) to select between LVPECL and LVDS signaling. A logic '0' configures LVPECL; '1' selects LVDS; NC (no connect) places the output in high-impedance state. Bank D also supports CMOS output (QD1) with independent slew rate control via SLEW_CMOS.

Does the PI6LC48S25AZBBIEX support I²C configuration during operation?

Yes - the device implements a full I²C slave interface (7-bit address DC_h/DE_h, configurable via I2C_ADR_SEL) supporting block read/write operations. All frequency, output enable, and signaling registers (Bytes 0–5) are writable in-system, enabling dynamic reconfiguration without reset or power cycle - essential for adaptive timing in software-defined networking.

What is the purpose of the X_OUT pin beyond crystal drive?

X_OUT provides a buffered, low-noise 25 MHz output derived directly from the internal crystal oscillator circuit - independent of the PLL path. This signal serves as a clean, low-jitter reference for auxiliary functions such as management microcontrollers, ADC/DAC clocks, or watchdog timers, eliminating the need for a separate crystal oscillator and reducing system-level phase noise coupling.

PI6LC48S25AZBBIEX Specifications

Product attributes: Attribute value

Manufacturer:: Diodes Incorporated

Series:: HiFlex™

Package/Case:: 56-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: Yes with Bypass

Main Purpose:: Ethernet

Input:: CMOS, LVPECL, Crystal

Output:: CMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 2:6

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 312.5MHz

Voltage - Supply:: 2.38V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 56-TQFN (8x8)

PI6LC48S25AZBBIEX FAQ

1.How can I place an order for PI6LC48S25AZBBIEX through Aetrix?

Please submit a Request for Quotation (RFQ) for PI6LC48S25AZBBIEX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for PI6LC48S25AZBBIEX reliable?

The price and inventory of PI6LC48S25AZBBIEX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PI6LC48S25AZBBIEX is usually 5 days.

3.What payment methods are accepted for PI6LC48S25AZBBIEX?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PI6LC48S25AZBBIEX transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for PI6LC48S25AZBBIEX?

PI6LC48S25AZBBIEX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your PI6LC48S25AZBBIEX order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for PI6LC48S25AZBBIEX?

For technical support, including PI6LC48S25AZBBIEX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PI6LC48S25AZBBIEX requirements.

6.How does Aetrix verify that PI6LC48S25AZBBIEX is sourced from the original manufacturer or authorized distributors?

All PI6LC48S25AZBBIEX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PI6LC48S25AZBBIEX meets industry standards.

7.What is the process for return or replacement of PI6LC48S25AZBBIEX?

All PI6LC48S25AZBBIEX units undergo pre-shipment inspection (PSI). If there is an issue with PI6LC48S25AZBBIEX, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The PI6LC48S25AZBBIEX part is unused and in its original packaging.

Return procedure for PI6LC48S25AZBBIEX:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

2026-08-11 LDO Regulator: Dropout Voltage, Noise, PSRR and Power Dissipation

LDO regulator guide covering low dropout voltage, power dissipation, thermal design, PSRR, output noise, capacitor stability, adjustable LDO circuits, LDO vs buck converter and datasheet selection chec…

2026-08-06 Conditional Access Module: CAM, CI/CI+ and DVB Security

Conditional Access Module guide covering CAM meaning, CI/CI+ interface, smart card authorization, DVB security workflow, TV and set-top box compatibility, internal electronics, ESD protection, connecto…

2026-08-03 Electronic Component Obsolescence: EOL Risks, Replacement Options and Last-Time Buy Strategy

Guide to electronic component obsolescence covering EOL risk, PCN/PDN notices, last-time buy planning, replacement options, form-fit-function validation, counterfeit risk and BOM lifecycle management.

2026-07-29 18650 Battery: Voltage, Capacity, Charging and Pack Design

18650 battery guide covering lithium-ion cell basics, 3.6V/3.7V voltage, 4.2V charging, mAh and Wh capacity, protected cells, chargers, BMS, series-parallel packs, holders, welding and sourcing checks.…

2026-07-27 Hall Effect Sensor: Working Principle, Types, Circuits and Applications

Hall effect sensor guide covering working principle, linear and digital sensors, Arduino circuits, current sensing, speed detection, automotive applications, A3144 examples, signal filtering and datash…

2026-07-20 Product Change Notification (PCN) in Electronic Components: Meaning and Supply Chain Response

Product Change Notification guide for electronic components, covering PCN meaning, PCN vs PDN/EOL, common change types, risk levels, form-fit-function review, engineering validation, BOM control, LTB/L…

2026-07-19 Blend Door Actuator: Symptoms, Location, Reset and Replacement Guide

A practical guide to blend door actuators, covering HVAC function, symptoms, location, AC and heater issues, reset and calibration, replacement cost, electrical diagnosis, compatibility checks, and rep…