Diodes Incorporated PI6LC58S1101ZDIEX

Overview

PI6LC58S1101 from Diodes Incorporated is a 11-output HiFlex™ Ethernet network clock generator featuring an LC-based PLL architecture, 3.3V supply, selectable LVPECL/LVDS outputs across four independent banks, and ultra-low RMS phase jitter of 0.08ps (156.25MHz, 10kHz–20MHz). It supports 25/50MHz crystal or differential reference inputs and targets high-speed networking systems including 10GbE, 40GbE, 100GbE, and 400GbE.

For engineers reviewing the PI6LC58S1101 datasheet, PI6LC58S1101 pinout, PI6LC58S1101 application, or PI6LC58S1101 equivalent, this device delivers deterministic low-jitter clock distribution with hardware-configurable output banks, industrial temperature operation (−40°C to +85°C), and high power supply noise rejection (−55dBc on VDDOx).

Technical Context

The PI6LC58S1101 implements a proprietary LC-VCO-based PLL with external loop filter (ICP/LFFR interface) enabling precise control over loop bandwidth and phase noise performance. Its four output banks (A–D) are independently configurable via 3-level control pins (NA[1:0], NB[1:0], NC[1:0], ND[1:0]) for frequency selection (e.g., 100/125/156.25/312.5MHz) and signaling type (LVPECL or LVDS).

Input flexibility includes dual-mode reference selection (IN+/IN− differential or X_IN/X_OUT crystal), with FREQ_IN pin selecting 25MHz or 50MHz input source. The device uses separate analog (VDDA, VDDA_XT, VDD_CP) and output (VDDOA–VDDOD) power domains to isolate noise-sensitive PLL circuitry from switching outputs.

Key Specifications

Pinout & Package

PI6LC58S1101 is housed in a 64-lead 9mm × 9mm TQFN package with exposed thermal pad (EPad) connected to GND. Pin layout supports segregated analog (VDDA, CAP_BIAS, LFF), core (VDD), clock input (X_IN/X_OUT, IN+/IN−), and per-bank output (QA–QD) and control (NA–ND, FREQ_IN, IN_SEL) domains.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Ethernet clock generator applications.

Compared with IDT8T49N242 and Si5341-A01, the PI6LC58S1101 offers deterministic hardware-based configuration, lowest measured RMS jitter (0.08ps), and optimal power supply noise rejection (−55dBc on VDDOx)-making it preferred for fixed-function, jitter-critical 10–400GbE line cards where startup simplicity and timing margin are paramount.

Availability

PI6LC58S1101 is available at Aetrix Electronics and suitable for 10GbE line cards, 40GbE switch fabric modules, and 100GbE optical transport equipment requiring stable component supply, long-term lifecycle support, and guaranteed industrial temperature performance.

Supply support for PI6LC58S1101 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for industrial, computing, and communications markets.

The PI6LC58S1101 belongs to Diodes' HiFlex™ clock generator product line, designed specifically for ultra-low-jitter Ethernet synchronization in multi-gigabit networking infrastructure-from access switches to core routers.

FAQ

What input reference sources does the PI6LC58S1101 support?

The PI6LC58S1101 supports two input modes: crystal oscillator (25MHz or 50MHz fundamental-mode, via X_IN/X_OUT pins) and differential clock (25MHz or 50MHz LVPECL/LVDS, via IN+/IN− pins). Selection is controlled by the IN_SEL pin (0 = crystal, 1 = differential). Crystal mode requires external load capacitors (C1/C2) and CAP_XTAL decoupling; differential mode uses internal 100Ω termination and VDD_CLK/2 bias.

How are output banks configured without software or I²C?

Each of the four output banks (A–D) is configured using dedicated 3-level control pins (e.g., NA[1:0], NB[1:0]). These pins accept Low/Middle/High voltage states via external resistive pullup/pulldown networks, directly selecting output signaling type (LVPECL or LVDS) and frequency (e.g., 100/125/156.25MHz). No register programming or communication interface is required-configuration is fully static and hardware-determined at power-up.

What is the purpose of the LFF and ICP pins?

LFF (pin 28) is the charge pump output node; ICP (pin 32) is the charge pump current input. Together they interface with an external passive loop filter (typically R2=150Ω, C1=200pF, C2=0.1μF) connected between LFF and LFFR (pin 27). This filter sets PLL loop bandwidth and stability-critical for achieving the specified −145dBc/Hz phase noise and 0.08ps RMS jitter performance.

Can unused output pins be left floating?

Yes-unused differential outputs (e.g., QB3+, QB3−) should be left open (NC) with no termination or routing. This minimizes EMI radiation and reduces supply current draw. Diodes recommends avoiding stub traces or unterminated lines longer than 5mm. For unused control pins (e.g., NC[0], NC[1]), internal pullup/pulldown resistors provide default states; adding 1kΩ resistors to GND adds robustness but is not mandatory.