Diodes Incorporated PI6PCIEB24ZDE

Overview

PI6PCIEB24ZDE from Pericom Semiconductor is a PCIe 2.0-compliant 1:4 differential clock driver with zero-delay PLL architecture, delivering four HCSL output pairs at 100 MHz, <50 ps cycle-to-cycle jitter, <1 ps additive RMS phase jitter, and ±250 ps propagation delay in PLL mode - deployed in server motherboard clock trees for CPU/PCIe slot synchronization.

For engineers reviewing the PI6PCIEB24ZDE datasheet, PI6PCIEB24ZDE pinout, PI6PCIEB24ZDE application, or PI6PCIEB24ZDE equivalent, key selection criteria include HCSL current-mode output compliance (IREF = 2.32 mA), PWRDWN#-controlled low-power state timing (<300 µs assertion, <1 ms stabilization), and TQFN-20 (4.0 × 4.0 mm) thermal performance under 85°C ambient.

Technical Context

The PI6PCIEB24ZDE implements a zero-delay PLL to regenerate PCIe 2.0 reference clocks while filtering input phase noise; it supports both PLL mode (PLL/BYPASS# = HIGH) and bypass mode (2.5–6.5 ns fixed delay). Its current-mode outputs drive 100 Ω differential loads with 0.7 V common-mode voltage and 6×IREF output current (13.9 mA nominal).

Power management includes active-Low PWRDWN# enabling dynamic current reduction to 40 mA, and separate VDD_A (PLL core) and VDD (output drivers) supplies for noise isolation. Input thresholds meet 3.3 V LVTTL logic levels (VIH ≥ 2.0 V, VIL ≤ 0.8 V), and IREF pin sets output current via external 475 Ω resistor.

Key Specifications

Pinout & Package

Package: 20-pin TQFN (ZD20), 4.0 mm × 4.0 mm × 0.75 mm, Pb-free and RoHS-compliant, with exposed thermal pad for PCB heat dissipation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe 2.0 clock buffer applications.

Compared with IDT8T49N242A and ICS843002AGI, the PI6PCIEB24ZDE offers native HCSL drive, programmable output gating, and lower power-down current - making it optimal for cost-sensitive, space-constrained PCIe 2.0 fanout where external clock sources are already present.

Availability

PI6PCIEB24ZDE is available at Aetrix Electronics and suitable for server motherboard design, industrial embedded computing platforms, and 5G baseband unit development requiring stable component supply and long-term lifecycle support.

Supply support for PI6PCIEB24ZDE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor was a fabless analog/mixed-signal IC designer specializing in high-speed timing, interface, and signal integrity solutions before its acquisition by Diodes Incorporated in 2017.

The PI6PCIEB24ZDE belongs to Pericom's PCIe clock buffer product line, engineered specifically for low-jitter, low-skew fanout in enterprise and communications infrastructure applications demanding PCIe 2.0 compliance.

FAQ

What is the function of the IREF pin on PI6PCIEB24ZDE?

The IREF pin sets the internal reference current for all HCSL output drivers via an external 475 Ω resistor. With VDD = 3.3 V, this yields 2.32 mA reference current, which scales output drive strength to 6×IREF (13.9 mA) per pin - ensuring consistent 0.7 V common-mode voltage into 100 Ω differential loads across temperature and voltage variations.

How does PWRDWN# affect output behavior during assertion?

When PWRDWN# is asserted (LOW), the PI6PCIEB24ZDE enters low-power mode: total supply current drops to 40 mA, and all outputs sink 2×IREF (4.64 mA) while presenting high impedance - preventing bus contention. Outputs stabilize within 1 ms after PWRDWN# de-assertion, meeting PCIe ASPM L1 substate timing requirements.

Can PI6PCIEB24ZDE operate in bypass mode, and what is its delay?

Yes - when PLL/BYPASS# is pulled LOW, the device operates in bypass mode with a fixed propagation delay of 2.5–6.5 ns (typical 4.5 ns). This mode eliminates PLL lock time and phase noise contribution but sacrifices jitter filtering; it is used when ultra-low latency is prioritized over input noise rejection.

What package type and thermal characteristics does PI6PCIEB24ZDE use?

PI6PCIEB24ZDE uses a 20-pin TQFN (ZD20) package measuring 4.0 mm × 4.0 mm × 0.75 mm with an exposed thermal pad. Its θ_JA is 42°C/W (JEDEC standard board), and maximum junction temperature is 125°C - supporting operation up to +85°C ambient when mounted on 2 oz copper with 4 thermal vias under the pad.