Diodes Incorporated PI6PCIEB24ZDEX

Overview

PI6PCIEB24ZDEX from Pericom Semiconductor is a PCIe 2.0-compliant 1:4 differential clock driver with zero-delay PLL architecture, delivering four HCSL output pairs at 100 MHz, <50 ps cycle-to-cycle jitter, <1 ps additive RMS phase jitter, and ±250 ps propagation delay in PLL mode. It serves as a timing distribution IC in server motherboard clock trees for CPU/PCIe slot synchronization.

For engineers reviewing the PI6PCIEB24ZDEX datasheet, PI6PCIEB24ZDEX pinout, PI6PCIEB24ZDEX application, or PI6PCIEB24ZDEX equivalent, key selection criteria include HCSL output compliance, PLL/bypass mode control, power-down sequencing timing (<300 µs assertion), IREF-set current accuracy (±12%), and TQFN-20 thermal performance under 85°C ambient.

Technical Context

The device implements a zero-delay PLL to regenerate PCIe 2.0 clocks with sub-50ps jitter while supporting bypass mode for direct signal pass-through. Its current-mode output buffers use external IREF (475Ω) to set 6×IREF = 13.9 mA nominal differential output current per pair.

Power management includes active-low PWRDWN# with fast de-assertion recovery (<1 ms stable), dual supply domains (VDD_A for PLL core, VDD for outputs), and independent OE_0/OE_3 enable controls per output pair - enabling dynamic clock gating in multi-slot PCIe topologies.

Key Specifications

Pinout & Package

Package: 20-pin 4.0 mm × 4.0 mm × 0.75 mm Pb-free TQFN (ZD20), thermal pad exposed on underside for PCB heat sinking.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe 2.0 clock distribution applications.

Compared with IDT 8V19N275 and ON Semi NB3N551, PI6PCIEB24ZDEX delivers native HCSL drive, lower additive jitter (<1 ps vs. ≥1.8 ps), and hardware-configurable PLL/bypass - making it optimal for PCIe 2.0 server clock trees requiring deterministic skew control and thermal resilience.

Availability

PI6PCIEB24ZDEX is available at Aetrix Electronics and suitable for server motherboard design, PCIe switch fanout, embedded computing backplanes, and industrial expansion chassis requiring stable component supply across extended temperature and long production lifecycles.

Supply support for PI6PCIEB24ZDEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor was a fabless provider specializing in high-speed interface and timing solutions before its acquisition by Diodes Incorporated in 2016; its timing portfolio remains widely deployed in enterprise infrastructure.

The PI6PCIEB24 product line targets PCIe 2.0 clock distribution in space-constrained, thermally demanding server and storage platforms - emphasizing jitter performance, HCSL compliance, and robust power management.

FAQ

What is the recommended IREF resistor value and tolerance for PI6PCIEB24ZDEX?

The datasheet specifies a 475Ω ±1% resistor connected between IREF (pin 16) and ground. This sets the reference current to 2.32 mA, which configures the current-mode output buffers to deliver 13.9 mA (6×IREF) per differential pair into 50Ω loads. Using tighter tolerance ensures output amplitude variation stays within ±12% of nominal.

Does PI6PCIEB24ZDEX support PCIe 3.0 or later generations?

No - PI6PCIEB24ZDEX is specified only for PCIe 2.0 compliance. Its 100 MHz fundamental input frequency, HCSL output swing, and additive jitter specification (<1 ps) align with PCIe Gen II requirements. It does not meet PCIe 3.0's 2.5 GHz signaling rate or SRIS jitter mask, and lacks equalization or spread-spectrum support required for Gen III+.

How is thermal management handled in the ZD20 TQFN package?

The ZD20 package features an exposed metal thermal pad on the underside that must be soldered to a large PCB copper pour connected to internal ground planes. Pericom's thermal characterization shows θ_JA = 32°C/W with 4 cm² 2-oz copper; this allows continuous operation at full load up to +85°C ambient when using ≥6 thermal vias under the pad.

Can PLL/BYPASS# and PWRDWN# be driven directly from FPGA GPIO pins?

Yes - both pins accept 3.3V LVTTL logic levels. PLL/BYPASS# has VIH ≥2.0V and VIL ≤0.8V; PWRDWN# has identical thresholds and draws <5 µA leakage. Standard FPGA I/O banks (e.g., Xilinx HP bank or Intel 3.3V LVCMOS) can drive them directly without level shifters, provided trace lengths are <15 mm to avoid ringing-induced false triggering.