Diodes Incorporated PI6ULS5V9517BUEX

Overview

PI6ULS5V9517BUEX from Diodes Incorporated is a dual-channel, bidirectional I²C/SMBus level-translating repeater IC enabling voltage translation between 0.8 V–5.5 V (Port A) and 2.2 V–5.5 V (Port B), supporting up to 400 kHz clock frequency with lock-up free operation, open-drain I/Os, and 5.5 V-tolerant enable and bus pins. It isolates bus capacitance and extends I²C topology in mixed-voltage embedded systems.

For engineers reviewing the PI6ULS5V9517BUEX datasheet, PI6ULS5V9517BUEX pinout, PI6ULS5V9517BUEX application, or PI6ULS5V9517BUEX equivalent, key selection considerations include port-specific supply ranges, propagation delay asymmetry (A→B vs. B→A), buffered low-level behavior on Port B, EN timing constraints (tSU/tH = 100 ns), and star vs. series topology compatibility.

Technical Context

The PI6ULS5V9517BUEX implements two independent bidirectional level-shifting channels using comparator-based input detection and CMOS output drivers powered solely by VCCB. Port A uses a 0.3×VCCA threshold for low-level detection to support sub-1.0 V logic, while Port B employs a 0.3×VCCB threshold plus hysteresis and a buffered ~0.5 V low output to prevent lock-up during arbitration.

It supports standard-mode and fast-mode I²C, preserves clock stretching and multi-master arbitration across ports, and requires external pull-up resistors-167 Ω (0.8–2.7 V) or 450 Ω (3.0–5.5 V) on Port A, 1.35 kΩ on Port B-with 57 pF load capacitance per side. EN must remain stable during active bus cycles to avoid bus hang.

Key Specifications

Pinout & Package

PI6ULS5V9517BUEX is packaged in an 8-pin MSOP (U) with 0.65 mm pitch, footprint-compatible with industry-standard SOIC-8 but with 30% smaller area and improved thermal performance. The package is RoHS-compliant, halogen-free, and tape-and-reel ready (X suffix).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I²C level-shifting repeater applications.

Compared with TCA9617A and PCA9517A, PI6ULS5V9517BUEX uniquely supports asymmetric 0.8 V ↔ 2.2 V translation with lock-up immunity, making it the only viable choice for next-generation ultra-low-power MCUs interfacing with legacy peripherals.

Availability

PI6ULS5V9517BUEX is available at Aetrix Electronics and suitable for industrial sensor hubs, automotive body control modules, medical wearable subsystems, and multi-rail power management systems requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for PI6ULS5V9517BUEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance, high-reliability components for power management, signal integrity, and connectivity applications.

The PI6ULS5V9517BUEX belongs to Diodes' Pericom® interface solutions portfolio, engineered specifically to solve mixed-voltage I²C/SMBus interoperability challenges in space-constrained, low-power embedded systems.

FAQ

Can PI6ULS5V9517BUEX operate with VCCA = 0.8 V and VCCB = 2.2 V simultaneously?

Yes. The device is explicitly characterized for this condition: Port A accepts 0.8 V–5.5 V, Port B accepts 2.2 V–5.5 V, and internal comparators use 0.3×VCCA and 0.3×VCCB thresholds. At these voltages, VOL on Port A is ≤0.2 V, ensuring reliable low-level detection by 0.8 V receivers, while Port B's ~0.5 V low remains above its 0.3×2.2 V = 0.66 V threshold - a design feature preventing lock-up.

What happens if EN is toggled during an active I²C transaction?

Toggling EN LOW mid-transaction forces both ports into high-impedance, halting SDA/SCL signaling and causing immediate bus hang - slave devices cannot complete ACK/NACK, and masters time out. The datasheet mandates EN state changes only during full bus idle (both lines HIGH for >1.3 ms). EN must remain HIGH throughout START, data, and STOP sequences to maintain protocol compliance.

Why does Port B output ~0.5 V instead of 0 V for LOW?

This buffered low is intentional: it keeps Port B's output voltage above the 0.3×VCCB input threshold (~0.66 V at 2.2 V), preventing the internal comparator from misinterpreting its own output as a valid low. This avoids positive feedback loops and ensures lock-up free arbitration - a critical differentiator versus basic MOSFET-based translators that lack hysteresis and dynamic threshold control.

Is PI6ULS5V9517BUEX compatible with I²C Fast-mode Plus (1 MHz)?

No. The device is rated for up to 400 kHz maximum clock frequency. While propagation delays (e.g., 67 ns A→B) suggest theoretical headroom, the datasheet explicitly limits operation to Fast-mode due to cumulative timing degradation from transition times (tTHL up to 175 ns), bus capacitance splitting constraints, and guaranteed arbitration preservation - Fast-mode Plus timing margins cannot be assured.