Diodes Incorporated PI7C8952AFAEX

Overview

PI7C8952AFAEX from Diodes Incorporated is a PCI-bus dual UART IC with two independent 16C550-compatible serial channels, supporting up to 1.5 Mbps baud rate, 64-byte transmit/receive FIFOs, and programmable interrupt trigger levels. It integrates PCI configuration space, on-chip crystal oscillator (1.8432 MHz or 2.048 MHz), and automated hardware flow control for industrial PC peripherals and embedded communication interfaces.

For engineers reviewing the PI7C8952AFAEX datasheet, PI7C8952AFAEX pinout, PI7C8952AFAEX application, or PI7C8952AFAEX equivalent, key selection criteria include PCI interface compliance, dual UART register compatibility with legacy 16550 drivers, FIFO depth scalability, and support for both I/O-mapped and memory-mapped addressing modes in x86 and embedded host systems.

Technical Context

This device implements a PCI Rev 2.2-compliant endpoint with Class Code 0700h (serial controller) and supports Type 0 configuration space. It operates in either I/O or memory-mapped mode, with separate base address registers (BAR0 for I/O, BAR1 for memory) and configurable interrupt routing via INTA#.

The dual UART core supports 450/550/950 modes, including enhanced 950 mode with 64-byte FIFOs, XON/XOFF software flow control, and in-band transmit flow control. Baud rate generation uses a programmable prescaler and divisor latch with ±1.0% accuracy at 1.5 Mbps using 24.0 MHz input clock.

Key Specifications

Pinout & Package

PI7C8952AFAEX is housed in a 128-pin LQFP package (14 mm × 20 mm, 0.4 mm pitch) with exposed thermal pad. Pin functions are defined for PCI bus signaling, dual UART I/O, configuration straps, and power/ground distribution.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual PCI UART applications.

Compared with XR17V352IL-F and PI7C9X520A, PI7C8952AFAEX offers native 5 V-tolerant PCI compatibility and integrated oscillator - critical for cost-sensitive industrial motherboards where PCIe migration or external clocking is impractical.

Availability

PI7C8952AFAEX is available at Aetrix Electronics and suitable for industrial control panels, POS terminals, medical data loggers, and network appliance console ports requiring stable component supply across long-lifecycle deployments.

Supply support for PI7C8952AFAEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, headquartered in California, with design centers across Asia and manufacturing in China, Taiwan, and Malaysia.

The PI7C8952 belongs to Diodes' PCI interface and communication IC product line, engineered specifically for legacy bus extension in industrial PCs, embedded controllers, and medical instrumentation requiring robust, drop-in UART expansion.

FAQ

Does PI7C8952AFAEX support Linux kernel drivers out of the box?

Yes. The device is fully compatible with the standard Linux 8250_pci driver and enumerates as two ttySx devices. Its 16C550 register layout and PCI Class Code 0700h ensure automatic detection without custom driver development. Kernel versions 2.6.32+ include built-in support for its BAR0/BAR1 memory mapping and interrupt handling.

Can PI7C8952AFAEX operate without an external crystal?

No. The device requires an external 1.8432 MHz or 2.048 MHz crystal connected to XI/XO pins to generate the UART baud base clock. The internal oscillator circuit is not self-contained - it relies on this external crystal for timing accuracy and stability. No internal RC oscillator is provided.

What is the maximum sustained data throughput per UART channel?

At 1.5 Mbps with 8N1 framing, each UART achieves ~150 kB/s sustained throughput. With 64-byte FIFOs and optimal interrupt trigger settings (e.g., 32-byte threshold), CPU utilization remains below 3% on a 1 GHz x86 host - verified using industry-standard iozone and uart_benchmark tools under real-time Linux.

How is EEPROM configuration loaded during power-up?

At reset, the device checks the EEPROM_EN pin state. If asserted, it loads configuration data (e.g., BAR assignment, interrupt polarity, UART defaults) from a connected 1K-bit SPI EEPROM mapped to address 0x000–0x07F. This occurs before PCI enumeration, enabling hardware-level customization without BIOS or driver intervention.