Diodes Incorporated PI90LV047ALEX

Overview

PI90LV047ALEX from Pericom Semiconductor is a quad LVDS line driver IC designed for high-speed point-to-point baseband data transmission over controlled-impedance media. It accepts TTL/CMOS input levels, delivers ±350 mV differential output into 100 Ω loads, supports >400 Mbps (200 MHz) data rates, features flow-through pinout, and operates from a 3.3 V supply across –40°C to +85°C.

For engineers reviewing the PI90LV047ALEX datasheet, PI90LV047ALEX pinout, PI90LV047ALEX application, or PI90LV047ALEX equivalent, key selection criteria include differential skew (≤400 ps), propagation delay (≤1.7 ns), 3-state enable control, LVDS compliance (TIA/EIA-644), and industrial temperature operation.

Technical Context

This device implements current-mode LVDS driver architecture with four independent differential channels. Each channel converts single-ended TTL/CMOS inputs to low-voltage differential outputs using matched current sources, ensuring precise V_OD = 350 mV ±50 mV and V_OS = 1.1–1.3 V under 3.3 V supply and 100 Ω termination.

The EN/EN enable pair controls simultaneous 3-state output disable across all channels, reducing idle power to 13 mW typical. Propagation delay matching between channels (t_SKD2 ≤ 400 ps) and edge alignment (t_SKD1 ≤ 300 ps) are guaranteed across voltage and temperature ranges.

Key Specifications

Pinout & Package

PI90LV047ALEX is packaged in a Pb-free, green 16-pin TSSOP (Package Code L), 4.4 mm × 5.0 mm body, 0.65 mm pitch, JEDEC MO-153F/AB compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad LVDS line driver applications.

Compared with SN65LVDS047DR and MAX9124ESE+, PI90LV047ALEX uniquely combines dual-enable 3-state control, lowest idle power (13 mW), and guaranteed flow-through layout - making it optimal for power-aware, high-density LVDS bus designs where timing alignment and layout simplicity are critical.

Availability

PI90LV047ALEX is available at Aetrix Electronics and suitable for flat panel display interfaces, machine vision camera links, medical imaging backplanes, and automotive ADAS video distribution requiring stable component supply and long-term manufacturability.

Supply support for PI90LV047ALEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (now part of Diodes Incorporated) specialized in high-speed interface solutions including LVDS, PCIe, USB, and clock management ICs before its 2016 acquisition.

The PI90LV047A belongs to Pericom's LVDS line driver product line, engineered specifically for low-power, high-fidelity parallel-to-differential conversion in display, imaging, and industrial video systems.

FAQ

What is the minimum load impedance required for stable PI90LV047ALEX operation?

The PI90LV047ALEX is specified for operation with 90 Ω to 110 Ω resistive termination across each differential pair. Driving into open-circuit or unterminated lines violates the current-mode architecture and causes undefined V_OD, excessive power dissipation, and potential damage. A 100 Ω Thevenin termination to V_CC/2 is recommended for DC-coupled systems.

Can PI90LV047ALEX drive 5 V LVDS receivers?

Yes - the PI90LV047ALEX is interoperable with legacy 5 V LVDS receivers per its datasheet. Its ±350 mV differential swing and common-mode voltage (~1.2 V) fall within the valid input range of TIA/EIA-644-compliant 5 V receivers, provided the receiver's common-mode input range includes 1.1–1.3 V and termination matches 100 Ω.

Is the EN/EN pin pair internally debounced or latched?

No - EN and EN are purely combinational control inputs with no internal debouncing, latching, or hysteresis. The truth table confirms that outputs transition to 3-state only when EN = LOW and EN = HIGH simultaneously. External RC filtering or synchronized control logic is required if enable signals originate from asynchronous sources.

Does PI90LV047ALEX require external biasing for AC-coupled LVDS links?

No - the device does not require external biasing on its outputs for AC-coupled operation. Its outputs are fully DC-balanced and self-biasing; however, the receiving end must provide proper common-mode termination (e.g., 100 Ω across D+ and D–, center-tapped to V_CC/2 or bias network) to establish correct common-mode voltage at the receiver input.