Diodes Incorporated PI90LV386AE

Overview

PI90LV386AE from Pericom Semiconductor is a 16-channel LVDS differential line receiver with 3-state outputs, designed for high-speed point-to-point data transmission over controlled-impedance media. It operates from a single 3.3V supply, supports signaling rates up to 660 Mbps, features ±100 mV differential input sensitivity, and delivers typical propagation delay of 2.6 ns with output skew under 100 ps - enabling precise timing alignment in backplane and PCB interconnect applications.

For engineers reviewing the PI90LV386AE datasheet, PI90LV386AE pinout, PI90LV386AE application, or PI90LV386AE equivalent, this device is selected for low-skew, high-density LVDS receiver functions in telecom infrastructure, industrial imaging systems, and high-resolution display interfaces where common-mode range (0–3 V), 3.3V compatibility, and 64-pin TSSOP packaging are critical.

Technical Context

The PI90LV386AE implements sixteen independent LVDS receivers compliant with ANSI TIA/EIA-644-1995, each accepting differential inputs within a 0–3 V common-mode range and producing LVTTL-compatible outputs. Each channel includes an individual enable (EN) pin supporting high-impedance tri-state control without bus loading.

It requires external 100-Ω termination resistors across each differential pair, distinguishing it from the integrated-termination PI90LVT386 variant. Timing performance is characterized across –40°C to +85°C, with part-to-part skew <1 ns and output skew ≤100 ps (typical), ensuring deterministic signal recovery in multi-lane parallel links.

Key Specifications

Pinout & Package

Package: 64-pin Thin Shrink Small Outline Package (TSSOP-A), Pb-free and RoHS-compliant, 240-mil body width, 0.5 mm lead pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS receiver applications.

Compared with PI90LVT386AE, the PI90LV386AE trades external termination flexibility for design control over resistor selection and placement; versus SN65LVDS32, it delivers 4× channel density and 65% higher speed in one package, reducing system-level skew and interconnect complexity.

Availability

PI90LV386AE is available at Aetrix Electronics and suitable for industrial imaging systems, telecom backplanes, medical console interfaces, and high-resolution display subsystems requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for PI90LV386AE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (now part of Diodes Incorporated) specialized in high-speed interface ICs, clock management, and signal integrity solutions for communications and computing markets.

The PI90LV386AE belongs to Pericom's LVDS receiver product line, engineered for low-skew, high-density parallel data reception in systems demanding precise timing alignment and robust noise immunity over extended PCB traces.

FAQ

What is the required termination configuration for PI90LV386AE?

The PI90LV386AE requires external 100-Ω termination resistors placed across each differential input pair (e.g., between RIN1+ and RIN1–). Unlike the PI90LVT386AE variant, it does not integrate termination resistors. This allows design flexibility in resistor selection (e.g., precision, power rating) and placement near the input nodes to minimize stub effects.

Can PI90LV386AE outputs drive 5V logic directly?

Yes - its LVTTL outputs are 5V-tolerant, meaning they can safely interface with 5V CMOS or TTL inputs without level-shifting circuitry. The outputs swing from GND to VCC (3.3V), but the input structures of downstream 5V devices recognize the 3.3V high-level as valid logic high, provided their VIH specification is ≤3.0V (standard for most 5V-tolerant inputs).

How does the enable pin architecture support partial channel shutdown?

The PI90LV386AE provides four independent EN pins (EN1–EN4), each controlling a group of four receivers. Asserting EN low disables the corresponding four outputs into high-impedance state, allowing selective channel gating without affecting other lanes - useful for power management in multi-sensor systems or dynamic bandwidth allocation in reconfigurable I/O architectures.

Is PI90LV386AE pin-compatible with PI90LVT386AE?

Yes - both share identical 64-pin TSSOP-A pinout, supply requirements, and functional behavior. The sole difference is internal termination: PI90LVT386AE integrates 110-Ω resistors, while PI90LV386AE requires external 100-Ω resistors. Swapping them requires updating the schematic to remove or retain external terminations accordingly.