NXP Semiconductors PIMXRT595SFFOA

Overview

PIMXRT595SFFOA from NXP Semiconductors is a dual-core low-power crossover processor featuring an Arm Cortex-M33 CPU (up to 275 MHz) and a Cadence Tensilica Fusion F1 DSP (up to 275 MHz), with 5 MB shared SRAM, on-the-fly AES decryption for FlexSPI, and hardware TrustZone security. It targets voice-enabled edge devices requiring concurrent real-time control and audio processing.

For engineers reviewing the PIMXRT595SFFOA datasheet, PIMXRT595SFFOA pinout, PIMXRT595SFFOA application, or PIMXRT595SFFOA equivalent, key selection criteria include dual-core asymmetric processing capability, integrated SRAM PUF and OTFAD, MIPI DSI support for display interfaces, and FOWLP249 package compatibility with high-density PCB layouts.

Technical Context

The PIMXRT595SFFOA implements a heterogeneous dual-domain architecture: the Cortex-M33 handles secure boot, system control, and real-time tasks with TrustZone isolation, while the Fusion F1 DSP executes low-latency audio preprocessing-including DMIC decimation, voice activation detection, and beamforming-using dedicated 8 KB SRAM banks. Both cores share access to 5 MB of low-leakage SRAM and two FlexSPI interfaces with 32 KB caches each.

Its power architecture supports five independent I/O rails (VDDIO_0/1/2/3/4), enabling direct interfacing with mixed-voltage peripherals; deep-sleep mode retains SRAM content at 0.6 V core voltage, and the DSP domain can be powered off independently while the M33 remains active for wake-up handling via RTC or OS/Event Timer interrupts.

Key Specifications

Pinout & Package

FOWLP249 (Fan-out Wafer-Level Package): 249-ball array, 0.4 mm pitch, 7.0 mm × 7.0 mm footprint, moisture sensitivity level (MSL) 3, compatible with standard reflow profiles per J-STD-020.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core crossover processor applications.

Compared with MIMXRT595SFFOC, PIMXRT595SFFOA provides identical silicon functionality and is suitable for engineering validation; compared with MIMXRT595SVFFOC, it omits pre-certified voice software but retains full hardware audio/DSP capability, giving designers flexibility to integrate custom or third-party voice stacks without licensing constraints.

Availability

PIMXRT595SFFOA is available at Aetrix Electronics and suitable for voice-enabled edge devices, industrial HMIs, and secure wearable medical monitors requiring stable component supply and long-term lifecycle support.

Supply support for PIMXRT595SFFOA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The i.MX RT500 series, including PIMXRT595SFFOA, was designed to bridge the gap between microcontrollers and application processors by integrating real-time determinism, ultra-low-power operation, and rich multimedia/audio capabilities in a single chip for intelligent edge endpoints.

FAQ

What is the maximum operating frequency of the Cortex-M33 core in PIMXRT595SFFOA?

The Cortex-M33 core in PIMXRT595SFFOA operates at up to 275 MHz under standard conditions. This maximum frequency requires VDDCORE ≥ 1.13 V during OTP programming and ≥ 1.0 V for initial power-on. In active mode with FBB enabled, the core runs stably across 0.7–1.155 V, with frequency scaling dynamically adjusted based on voltage and temperature.

Does PIMXRT595SFFOA support secure boot from external flash?

Yes, PIMXRT595SFFOA supports secure boot from external flash via its FlexSPI interface with on-the-fly AES decryption (OTFAD). The ROM bootloader validates signed images and enables execute-in-place (XIP) from encrypted flash without exposing decrypted code in SRAM, meeting PSA Level 3 and SESIP Level 3 security requirements.

What package type and dimensions does PIMXRT595SFFOA use?

PIMXRT595SFFOA uses the FOWLP249 package: a 249-ball fan-out wafer-level package measuring 7.0 mm × 7.0 mm × 0.725 mm with 0.4 mm ball pitch. It has moisture sensitivity level (MSL) 3 and complies with JEDEC J-STD-020 reflow standards for lead-free assembly.

Can the DSP core in PIMXRT595SFFOA operate independently of the Cortex-M33?

Yes, the Cadence Tensilica Fusion F1 DSP in PIMXRT595SFFOA can run autonomously while the Cortex-M33 is in sleep or deep-sleep mode. The DSP domain has independent power control and retains its clock domain, enabling continuous audio monitoring or sensor fusion without waking the M33 - critical for ultra-low-power always-on applications.

How many digital microphone channels does PIMXRT595SFFOA support, and what preprocessing is hardware-accelerated?

PIMXRT595SFFOA supports up to 8 digital microphone (DMIC) channels with fully hardware-accelerated preprocessing: PDM-to-PCM decimation, voice activity detection (VAD), and channel synchronization. Each DMIC input includes dedicated decimator logic and FIFO, offloading >90% of audio preprocessing from both CPU cores and enabling sub-100 µs wake-word latency.