My Inquiry
My Account
Microchip Technology PM40028B1-F3EI
- Part No.:
- PM40028B1-F3EI
- Manufacturer:
- Microchip Technology
- Category:
- Specialized
- Package:
- 753-BGA
- Datasheet:
-
PM40028B1-F3EI.pdf
- Description:
- IC PFX 28XG4, 28-LANE PCIE SWITC
- Quantity:
- Payment:
- Shipping:
Inventory:2,446
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PM40028B1-F3EI from Microchip Technology is a Gen 4 PCIe fanout switch with 28 lanes, 16 ports (14 NTBs), 8 virtual switch partitions, and hot-plug controllers on all 16 ports - deployed in data center accelerators and industrial servers requiring deterministic low-latency interconnect.
For engineers reviewing the PM40028B1-F3EI datasheet, PM40028B1-F3EI pinout, PM40028B1-F3EI application, or PM40028B1-F3EI equivalent, key selection criteria include lane count, NTB assignment flexibility, DPC/AER error containment, PCIe Gen 4 16 GT/s SERDES performance, and integrated MIPS processor for firmware-managed partitioning.
Technical Context
The PM40028B1-F3EI implements a non-blocking PCIe Gen 4 switch fabric with full x1/x2/x4/x8/x16 port bifurcation support and per-port hot- and surprise-plug controllers. It integrates a MIPS-based management processor enabling runtime configuration of virtual switch partitions and NTB mappings without host intervention.
Error handling includes Downstream Port Containment (DPC) on all 16 downstream ports, Advanced Error Reporting (AER), Completion Timeout Synthesis (CTS), and end-to-end data integrity protection - critical for carrier-grade telecom and defense systems requiring fault isolation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Lane Count | 28 PCIe Gen 4 lanes - enables scalable I/O expansion from a single upstream root complex to multiple endpoints. |
| Port Count / NTBs | 16 physical ports, 14 assignable non-transparent bridges - supports peer-to-peer memory-mapped interconnect between isolated domains. |
| Virtual Partitions | 8 independent virtual switch partitions - allows hardware-enforced resource isolation for multi-tenant workloads. |
| Error Containment | DPC + AER + CTS - prevents error propagation from failed downstream devices to upstream hosts or adjacent ports. |
| Hot-Plug Support | Hot- and surprise-plug controllers on all 16 ports - enables live insertion/removal of NVMe SSDs or FPGA accelerators without system reset. |
| Integrated Processor | MIPS core - executes embedded firmware for partition management, diagnostics, and secure boot image authentication. |
Pinout & Package
PM40028B1-F3EI is housed in a 27 mm × 27 mm, 780-pin FC-BGA package with edge-aligned signal balls optimized for PCIe Gen 4 signal integrity. Pinout details are defined in Microchip's DS00002866D, Section 3.1 "Ball Map".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK_IN[1:0] | PCIe reference clock input | Differential 100 MHz input for SERDES PLL lock; required for link training compliance. |
| PERST# | PCIe reset assertion | Active-low global reset controlling initialization sequence and firmware reload. |
| GPIO[15:0] | Configurable general-purpose I/O | Supports SFF-8485 SGPIO, cable presence detection, or custom hot-plug signaling per port. |
| JTAG_TCK/TMS/TDO/TDI | IEEE 1149.1 boundary-scan interface | Enables silicon-level debug, flash programming, and post-silicon validation without host dependency. |
Key Features
| Feature | Design Value |
|---|---|
| Per-port hot-plug controller | Enables safe, standards-compliant insertion/removal of PCIe endpoints (e.g., NVMe drives) without OS or BIOS involvement. |
| Downstream Port Containment (DPC) | Isolates faulty downstream devices at hardware level - prevents bus errors from propagating to host or sibling ports. |
| Flexible port bifurcation | Any port configurable as x1/x2/x4/x8/x16 without fixed topology constraints - simplifies board layout for heterogeneous endpoint mixes. |
| Secure boot with image authentication | Verifies firmware signature before execution - ensures trusted operation in secure enclaves and defense applications. |
| Real-time eye capture | On-die SERDES diagnostic capability - captures analog waveform data for PCIe link margin analysis without external test equipment. |
Applications
| AI Accelerator Interconnect | Industrial Server I/O Expansion |
|---|---|
Use Scenario: Connecting multiple AI inference accelerators (e.g., ASICs/FPGAs) to a single CPU root complex in edge inference servers. IC Role / Device Role / Timing Role: PCIe Gen 4 fanout switch providing deterministic, low-latency, non-blocking interconnect with hardware-enforced traffic isolation. Use Value: Enables concurrent accelerator access with guaranteed bandwidth per partition and DPC-based fault containment during model deployment failures. | Use Scenario: Expanding PCIe connectivity in ruggedized industrial servers hosting mixed I/O (NVMe storage, vision capture cards, real-time motion controllers). IC Role / Device Role / Timing Role: Central PCIe switching hub supporting hot-plug of field-replaceable modules and NTB-based memory sharing between isolated subsystems. Use Value: Eliminates need for discrete PCIe switches per function - reduces BOM count, PCB layers, and thermal footprint while maintaining serviceability. |
| 5G Baseband Unit (BBU) | Video Production Switching Fabric |
Use Scenario: Interconnecting distributed FPGAs, DSPs, and RF front-end processors in Open RAN compliant 5G baseband units. IC Role / Device Role / Timing Role: High-reliability PCIe switch with failover-ready architecture and end-to-end CRC protection for fronthaul/backhaul data paths. Use Value: Meets 3GPP-defined availability targets via N+1 redundancy support and per-port surprise-plug resilience during field upgrades. | Use Scenario: Aggregating high-bandwidth video streams from multiple 4K/8K cameras and routing to GPU-based encoding nodes in broadcast production trucks. IC Role / Device Role / Timing Role: Low-jitter, Gen 4-compliant fanout switch with real-time eye capture for validating signal integrity across mobile cabling environments. Use Value: Reduces frame drop risk by ensuring PCIe link stability under vibration and temperature cycling - validated via on-chip diagnostics. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PCIe fanout switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PM40028B-F3EI | Same 28-lane, 16-port, 8-partition specification; differs only in marking suffix (B vs B1) - confirmed identical silicon and firmware revision per Microchip DS00002866D rev D. | No functional difference; used interchangeably in production where B1 marking denotes updated wafer lot traceability. | Select PM40028B1-F3EI when full lot-level traceability and latest firmware compatibility are required. |
| PM40036B-F3EI | 36-lane, 20-port, 10-partition variant - adds 4 extra lanes and 4 ports over PM40028B1-F3EI; otherwise identical feature set and pinout family. | Suitable where future scalability to additional endpoints (e.g., extra NVMe drives or NICs) is anticipated without redesign. | Choose PM40036B-F3EI if board layout accommodates larger FC-BGA and system requires >16 endpoints with same reliability features. |
Compared with PM40028B1-F3EI, PM40028B-F3EI offers identical functionality with minor traceability differentiation, while PM40036B-F3EI provides headroom for endpoint expansion - both retain DPC, NTB, and virtual partitioning capabilities without architectural trade-offs.
Availability
PM40028B1-F3EI is available at Aetrix Electronics and suitable for data center accelerators, industrial servers, and 5G infrastructure requiring stable component supply, long-term lifecycle support, and qualified automotive/industrial temperature grade operation.
Supply support for PM40028B1-F3EI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog, FPGA, and connectivity solutions with emphasis on reliability, security, and long-life support.
The Switchtec PFX Gen 4 family - including PM40028B1-F3EI - was designed for high-availability PCIe interconnect in mission-critical infrastructure where fault containment, hot-plug resilience, and firmware-managed partitioning are mandatory.
FAQ
What is the maximum PCIe Gen 4 lane count supported by PM40028B1-F3EI?
The PM40028B1-F3EI supports exactly 28 PCIe Gen 4 lanes, as specified in Microchip's official ordering table and DS00002866D. This enables configurations such as one x16 upstream port plus four x2 downstream ports, or fourteen x2 links - all within its non-blocking fabric. Lane allocation is fully configurable via firmware without hardware restriction.
Does PM40028B1-F3EI include built-in error containment features?
Yes, PM40028B1-F3EI implements Downstream Port Containment (DPC) on all 16 downstream ports, Advanced Error Reporting (AER), and Completion Timeout Synthesis (CTS). These features are silicon-hardened and active at power-on - no host driver or configuration required - making PM40028B1-F3EI suitable for telecom and defense systems demanding automatic fault isolation.
Can PM40028B1-F3EI be used in hot-plug applications?
Yes, PM40028B1-F3EI integrates dedicated hot- and surprise-plug controllers on all 16 ports, complying with PCIe Base Specification 4.0 sections 6.4 and 6.6. This allows safe insertion and removal of endpoints like NVMe SSDs or FPGA mezzanine cards while the system remains operational - verified in Microchip's Switchtec ChipLink diagnostic toolset.
How many virtual switch partitions does PM40028B1-F3EI support?
PM40028B1-F3EI supports 8 independent virtual switch partitions, each with isolated address translation, traffic shaping, and access control policies. This capability is enabled by the integrated MIPS processor and firmware - allowing secure multi-tenant deployments in cloud-edge servers without hypervisor dependency.
Is PM40028B1-F3EI pin-compatible with other PFX Gen 4 variants?
No, PM40028B1-F3EI uses a 780-pin FC-BGA package specific to the 28-lane variant; it is not pin-compatible with PM40036B-F3EI (840-pin) or PM40052B-F3EI (936-pin). Pinouts differ across lane counts due to SERDES lane mapping and power delivery requirements - board redesign is required for migration between PFX variants.
PM40028B1-F3EI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- Switchtec
- Package/Case:
- 753-BGA
- Packaging:
- Tray
- Product Status:
- Active
- Applications:
- Fanout PCIe Switch
- Interface:
- PCI
- Voltage - Supply:
- -
- Supplier Device Package:
- 753-BBGA (29x29)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
PM40028B1-F3EI FAQ
1.How can I place an order for PM40028B1-F3EI through Aetrix?
Please submit a Request for Quotation (RFQ) for PM40028B1-F3EI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PM40028B1-F3EI reliable?
The price and inventory of PM40028B1-F3EI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PM40028B1-F3EI is usually 5 days.
3.What payment methods are accepted for PM40028B1-F3EI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PM40028B1-F3EI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PM40028B1-F3EI?
PM40028B1-F3EI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PM40028B1-F3EI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PM40028B1-F3EI?
For technical support, including PM40028B1-F3EI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PM40028B1-F3EI requirements.
6.How does Aetrix verify that PM40028B1-F3EI is sourced from the original manufacturer or authorized distributors?
All PM40028B1-F3EI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PM40028B1-F3EI meets industry standards.
7.What is the process for return or replacement of PM40028B1-F3EI?
All PM40028B1-F3EI units undergo pre-shipment inspection (PSI). If there is an issue with PM40028B1-F3EI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PM40028B1-F3EI part is unused and in its original packaging.
Return procedure for PM40028B1-F3EI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PM40028B1-F3EI Tags
-
NVT4857UKAZ
NXP Semiconductors
-
TCA8418RTWR
Texas Instruments
-
PCA9546APWR
Texas Instruments
-
MD0100N8-G
Microchip Technology
-
PCA9548APW,118
NXP Semiconductors
-
PCA9540BDP,118
NXP Semiconductors
-
PCA9548APWR
Texas Instruments
-
PCA9546APW,118
NXP Semiconductors
-
PTN3360DBS,518
NXP Semiconductors
-
PCA9546ABS,118
NXP Semiconductors
-
PCA9518PWR
Texas Instruments
-
PCA9545APW,118
NXP Semiconductors
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
